Documentation/iio/ad7191.rst

Source file repositories/reference/linux-study-clean/Documentation/iio/ad7191.rst

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Documentation/iio/ad7191.rst
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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.. SPDX-License-Identifier: GPL-2.0-only

=============
AD7191 driver
=============

Device driver for Analog Devices AD7191 ADC.

Supported devices
=================

* `AD7191 <https://www.analog.com/AD7191>`_

The AD7191 is a high precision, low noise, 24-bit Σ-Δ ADC with integrated PGA.
It features two differential input channels, an internal temperature sensor, and
configurable sampling rates.

Devicetree
==========

Pin Configuration
-----------------

The driver supports both pin-strapped and GPIO-controlled configurations for ODR
(Output Data Rate) and PGA (Programmable Gain Amplifier) settings. These
configurations are mutually exclusive - you must use either pin-strapped or GPIO
control for each setting, not both.

ODR Configuration
^^^^^^^^^^^^^^^^^

The ODR can be configured either through GPIO control or pin-strapping:

- When using GPIO control, specify the "odr-gpios" property in the device tree
- For pin-strapped configuration, specify the "adi,odr-value" property in the
  device tree

Available ODR settings:

  - 120 Hz (ODR1=0, ODR2=0)
  - 60 Hz (ODR1=0, ODR2=1)
  - 50 Hz (ODR1=1, ODR2=0)
  - 10 Hz (ODR1=1, ODR2=1)

PGA Configuration
^^^^^^^^^^^^^^^^^

The PGA can be configured either through GPIO control or pin-strapping:

- When using GPIO control, specify the "pga-gpios" property in the device tree
- For pin-strapped configuration, specify the "adi,pga-value" property in the
  device tree

Available PGA gain settings:

  - 1x (PGA1=0, PGA2=0)
  - 8x (PGA1=0, PGA2=1)
  - 64x (PGA1=1, PGA2=0)
  - 128x (PGA1=1, PGA2=1)

Clock Configuration
-------------------

The AD7191 supports both internal and external clock sources:

- When CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property
  needed)
- When CLKSEL pin is INACTIVE: Requires external clock source
  - Can be a crystal between MCLK1 and MCLK2 pins
  - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected

Annotation

Implementation Notes