Documentation/power/powercap/powercap.rst
Source file repositories/reference/linux-study-clean/Documentation/power/powercap/powercap.rst
File Facts
- System
- Linux kernel
- Corpus path
Documentation/power/powercap/powercap.rst- Extension
.rst- Size
- 10619 bytes
- Lines
- 263
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: documentation
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
=======================
Power Capping Framework
=======================
The power capping framework provides a consistent interface between the kernel
and the user space that allows power capping drivers to expose the settings to
user space in a uniform way.
Terminology
===========
The framework exposes power capping devices to user space via sysfs in the
form of a tree of objects. The objects at the root level of the tree represent
'control types', which correspond to different methods of power capping. For
example, the intel-rapl control type represents the Intel "Running Average
Power Limit" (RAPL) technology, whereas the 'idle-injection' control type
corresponds to the use of idle injection for controlling power.
Power zones represent different parts of the system, which can be controlled and
monitored using the power capping method determined by the control type the
given zone belongs to. They each contain attributes for monitoring power, as
well as controls represented in the form of power constraints. If the parts of
the system represented by different power zones are hierarchical (that is, one
bigger part consists of multiple smaller parts that each have their own power
controls), those power zones may also be organized in a hierarchy with one
parent power zone containing multiple subzones and so on to reflect the power
control topology of the system. In that case, it is possible to apply power
capping to a set of devices together using the parent power zone and if more
fine grained control is required, it can be applied through the subzones.
Example sysfs interface tree::
/sys/devices/virtual/powercap
└──intel-rapl
├──intel-rapl:0
│ ├──constraint_0_name
│ ├──constraint_0_power_limit_uw
│ ├──constraint_0_time_window_us
│ ├──constraint_1_name
│ ├──constraint_1_power_limit_uw
│ ├──constraint_1_time_window_us
│ ├──device -> ../../intel-rapl
│ ├──energy_uj
│ ├──intel-rapl:0:0
│ │ ├──constraint_0_name
│ │ ├──constraint_0_power_limit_uw
│ │ ├──constraint_0_time_window_us
│ │ ├──constraint_1_name
│ │ ├──constraint_1_power_limit_uw
│ │ ├──constraint_1_time_window_us
│ │ ├──device -> ../../intel-rapl:0
│ │ ├──energy_uj
│ │ ├──max_energy_range_uj
│ │ ├──name
│ │ ├──enabled
│ │ ├──power
│ │ │ ├──async
│ │ │ []
│ │ ├──subsystem -> ../../../../../../class/power_cap
│ │ └──uevent
│ ├──intel-rapl:0:1
│ │ ├──constraint_0_name
│ │ ├──constraint_0_power_limit_uw
│ │ ├──constraint_0_time_window_us
│ │ ├──constraint_1_name
│ │ ├──constraint_1_power_limit_uw
│ │ ├──constraint_1_time_window_us
│ │ ├──device -> ../../intel-rapl:0
│ │ ├──energy_uj
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.