Documentation/spi/multiple-data-lanes.rst

Source file repositories/reference/linux-study-clean/Documentation/spi/multiple-data-lanes.rst

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Documentation/spi/multiple-data-lanes.rst
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====================================
SPI devices with multiple data lanes
====================================

Some specialized SPI controllers and peripherals support multiple data lanes
that allow reading more than one word at a time in parallel. This is different
from dual/quad/octal SPI where multiple bits of a single word are transferred
simultaneously.

For example, controllers that support parallel flash memories have this feature
as do some simultaneous-sampling ADCs where each channel has its own data lane.

---------------------
Describing the wiring
---------------------

The ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the devicetree
are used to describe how many data lanes are connected between the controller
and how wide each lane is. The number of items in the array indicates how many
lanes there are, and the value of each item indicates how many bits wide that
lane is.

For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be
wired up like this::

    +--------------+    +----------+
    | SPI          |    | AD4630   |
    | Controller   |    | ADC      |
    |              |    |          |
    |          CS0 |--->| CS       |
    |          SCK |--->| SCK      |
    |          SDO |--->| SDI      |
    |              |    |          |
    |        SDIA0 |<---| SDOA0    |
    |        SDIA1 |<---| SDOA1    |
    |        SDIA2 |<---| SDOA2    |
    |        SDIA3 |<---| SDOA3    |
    |              |    |          |
    |        SDIB0 |<---| SDOB0    |
    |        SDIB1 |<---| SDOB1    |
    |        SDIB2 |<---| SDOB2    |
    |        SDIB3 |<---| SDOB3    |
    |              |    |          |
    +--------------+    +----------+

It is described in a devicetree like this::

    spi {
        compatible = "my,spi-controller";

        ...

        adc@0 {
            compatible = "adi,ad4630";
            reg = <0>;
            ...
            spi-rx-bus-width = <4>, <4>; /* 2 lanes of 4 bits each */
            ...
        };
    };

In most cases, lanes will be wired up symmetrically (A to A, B to B, etc). If
this isn't the case, extra ``spi-rx-lane-map`` and ``spi-tx-lane-map``
properties are needed to provide a mapping between controller lanes and the
physical lane wires.

Here is an example where a multi-lane SPI controller has each lane wired to
separate single-lane peripherals::

    +--------------+    +----------+

Annotation

Implementation Notes