Documentation/translations/zh_CN/mm/damon/faq.rst
Source file repositories/reference/linux-study-clean/Documentation/translations/zh_CN/mm/damon/faq.rst
File Facts
- System
- Linux kernel
- Corpus path
Documentation/translations/zh_CN/mm/damon/faq.rst- Extension
.rst- Size
- 1020 bytes
- Lines
- 32
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: documentation
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
.. SPDX-License-Identifier: GPL-2.0
:Original: Documentation/mm/damon/faq.rst
:翻译:
司延腾 Yanteng Si <siyanteng@loongson.cn>
:校译:
========
常见问题
========
DAMON是否只支持虚拟内存?
=========================
不,DAMON的核心是独立于地址空间的。用户可以在DAMON核心上实现和配置特定地址空间的低级原始
部分,包括监测目标区域的构造和实际的访问检查。通过这种方式,DAMON用户可以用任何访问检查技
术来监测任何地址空间。
尽管如此,DAMON默认为虚拟内存和物理内存提供了基于vma/rmap跟踪和PTE访问位检查的地址空间
相关功能的实现,以供参考和方便使用。
我可以简单地监测页面的粒度吗?
==============================
是的,你可以通过设置 ``min_nr_regions`` 属性高于工作集大小除以页面大小的值来实现。
因为监视目标区域的大小被强制为 ``>=page size`` ,所以区域分割不会产生任何影响。
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.