drivers/accel/amdxdna/aie2_message.c
Source file repositories/reference/linux-study-clean/drivers/accel/amdxdna/aie2_message.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/amdxdna/aie2_message.c- Extension
.c- Size
- 33931 bytes
- Lines
- 1271
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/amdxdna_accel.hdrm/drm_cache.hdrm/drm_device.hdrm/drm_gem.hdrm/drm_gem_shmem_helper.hdrm/drm_print.hdrm/gpu_scheduler.hlinux/bitfield.hlinux/errno.hlinux/pci.hlinux/types.hlinux/xarray.haie.haie2_msg_priv.haie2_pci.hamdxdna_ctx.hamdxdna_gem.hamdxdna_mailbox.hamdxdna_mailbox_helper.hamdxdna_pci_drv.h
Detected Declarations
function Copyrightfunction aie2_resume_fwfunction aie2_set_runtime_cfgfunction aie2_get_runtime_cfgfunction aie2_assign_mgmt_pasidfunction aie2_query_aie_versionfunction aie2_query_aie_metadatafunction aie2_query_firmware_versionfunction aie2_destroy_context_reqfunction aie2_get_context_priorityfunction aie2_create_contextfunction aie2_destroy_contextfunction aie2_send_host_buf_msgsfunction aie2_map_host_buffunction aie2_add_host_buffunction amdxdna_hwctx_col_mapfunction aie2_query_statusfunction aie2_query_telemetryfunction aie2_register_asyn_event_msgfunction aie2_config_cufunction aie2_init_exec_cu_reqfunction aie2_init_exec_dpu_reqfunction aie2_init_exec_chain_reqfunction aie2_init_npu_chain_reqfunction aie2_cmdlist_fill_cffunction aie2_cmdlist_fill_dpufunction aie2_cmdlist_unsuppfunction aie2_get_chain_msg_opfunction aie2_cmdlist_fill_npu_cffunction aie2_cmdlist_fill_npu_dpufunction aie2_cmdlist_fill_npu_preemptfunction aie2_cmdlist_fill_npu_elffunction aie2_get_npu_chain_msg_opfunction aie2_init_exec_reqfunction aie2_cmdlist_fill_slotfunction aie2_msg_initfunction aie2_cmdlist_get_cmd_buffunction aie2_execbuffunction aie2_cmdlist_multi_execbuffunction aie2_cmdlist_single_execbuffunction aie2_sync_bofunction aie2_config_debug_bofunction aie2_query_app_healthfunction aie2_runtime_update_ctx_propfunction aie2_update_prop_time_quotafunction aie2_get_dev_revision
Annotated Snippet
if (ret) {
XDNA_ERR(xdna, "failed to enable force preempt %d", ret);
goto del_ctx_req;
}
}
cq_pair = &resp.cq_pair[0];
x2i.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.head_addr);
x2i.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.tail_addr);
x2i.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->x2i_q.buf_addr);
x2i.rb_size = cq_pair->x2i_q.buf_size;
i2x.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.head_addr);
i2x.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.tail_addr);
i2x.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->i2x_q.buf_addr);
i2x.rb_size = cq_pair->i2x_q.buf_size;
ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id);
if (ret == -EINVAL) {
XDNA_ERR(xdna, "Alloc IRQ failed %d", ret);
goto del_ctx_req;
}
intr_reg = i2x.mb_head_ptr_reg + 4;
hwctx->priv->mbox_chann = xdna_mailbox_alloc_channel(ndev->mbox);
if (!hwctx->priv->mbox_chann) {
XDNA_ERR(xdna, "Not able to create channel");
ret = -EINVAL;
goto del_ctx_req;
}
ret = xdna_mailbox_start_channel(hwctx->priv->mbox_chann, &x2i, &i2x,
intr_reg, ret);
if (ret) {
XDNA_ERR(xdna, "Not able to create channel");
ret = -EINVAL;
goto free_channel;
}
ndev->hwctx_num++;
XDNA_DBG(xdna, "Mailbox channel irq: %d, msix_id: %d", ret, resp.msix_id);
XDNA_DBG(xdna, "Created fw ctx %d pasid %d", hwctx->fw_ctx_id, hwctx->client->pasid);
return 0;
free_channel:
xdna_mailbox_free_channel(hwctx->priv->mbox_chann);
del_ctx_req:
aie2_destroy_context_req(ndev, hwctx->fw_ctx_id);
return ret;
}
int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx)
{
struct amdxdna_dev *xdna = ndev->aie.xdna;
int ret;
if (!hwctx->priv->mbox_chann)
return 0;
xdna_mailbox_stop_channel(hwctx->priv->mbox_chann);
ret = aie2_destroy_context_req(ndev, hwctx->fw_ctx_id);
xdna_mailbox_free_channel(hwctx->priv->mbox_chann);
XDNA_DBG(xdna, "Destroyed fw ctx %d", hwctx->fw_ctx_id);
hwctx->priv->mbox_chann = NULL;
hwctx->fw_ctx_id = -1;
ndev->hwctx_num--;
return ret;
}
static int aie2_send_host_buf_msgs(struct amdxdna_dev_hdl *ndev, u32 context_id,
u64 addr, u64 size, u32 initial_opcode)
{
DECLARE_AIE_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER);
struct amdxdna_dev *xdna = ndev->aie.xdna;
size_t chunk_size;
int ret;
chunk_size = xdna->dev_info->dev_mem_size;
if (!size || !IS_ALIGNED(size, chunk_size)) {
XDNA_ERR(xdna, "Invalid size 0x%llx for chunk 0x%lx",
size, chunk_size);
return -EINVAL;
}
msg.opcode = initial_opcode;
do {
req.context_id = context_id;
req.buf_addr = addr;
Annotation
- Immediate include surface: `drm/amdxdna_accel.h`, `drm/drm_cache.h`, `drm/drm_device.h`, `drm/drm_gem.h`, `drm/drm_gem_shmem_helper.h`, `drm/drm_print.h`, `drm/gpu_scheduler.h`, `linux/bitfield.h`.
- Detected declarations: `function Copyright`, `function aie2_resume_fw`, `function aie2_set_runtime_cfg`, `function aie2_get_runtime_cfg`, `function aie2_assign_mgmt_pasid`, `function aie2_query_aie_version`, `function aie2_query_aie_metadata`, `function aie2_query_firmware_version`, `function aie2_destroy_context_req`, `function aie2_get_context_priority`.
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.