drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/gaudi2/gaudi2_coresight_regs.h- Extension
.h- Size
- 29046 bytes
- Lines
- 1064
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
gaudi2_masks.h../include/gaudi2/gaudi2_coresight.hgaudi2P.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef GAUDI2_CORESIGHT_REGS_DRV_H_
#define GAUDI2_CORESIGHT_REGS_DRV_H_
#include "gaudi2_masks.h"
#include "../include/gaudi2/gaudi2_coresight.h"
#include "gaudi2P.h"
/* FUNNEL Offsets - same offsets for all funnels*/
#define mmFUNNEL_CTRL_REG_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PRIORITY_CTRL_REG_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_ITATBDATA0_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_ITATBCTR2_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_ITATBCTR1_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_ITATBCTR0_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_ITCTRL_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_ITCTRL - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_CLAIMSET_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_CLAIMCLR_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_LOCKACCESS_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_LOCKSTATUS_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_AUTHSTATUS_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_DEVID_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_DEVID - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_DEVTYPE_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PIDR4_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PIDR4 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PERIPHID5_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PERIPHID6_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PERIPHID7_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PIDR0_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PIDR0 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PIDR1_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PIDR1 - \
mmDCORE0_TPC0_EML_FUNNEL_BASE)
#define mmFUNNEL_PIDR2_OFFSET \
(mmDCORE0_TPC0_EML_FUNNEL_PIDR2 - \
Annotation
- Immediate include surface: `gaudi2_masks.h`, `../include/gaudi2/gaudi2_coresight.h`, `gaudi2P.h`.
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.