drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/gaudi2/gaudi2_masks.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/gaudi2/gaudi2_masks.h
Extension
.h
Size
6462 bytes
Lines
162
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef GAUDI2_MASKS_H_
#define GAUDI2_MASKS_H_

#include "../include/gaudi2/asic_reg/gaudi2_regs.h"

/* Useful masks for bits in various registers */
#define QMAN_GLBL_ERR_CFG_MSG_EN_MASK	\
	((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))

#define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	\
	((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT))

#define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK	\
	(0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT)

#define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK	\
	((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT))

#define QM_PQC_LBW_WDATA	\
	((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \
	(1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT))

#define QMAN_MAKE_TRUSTED	\
	((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))

#define QMAN_MAKE_TRUSTED_TEST_MODE	\
	((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \
	(0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \
	(0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \
	(0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT))

#define QMAN_ENABLE		\
	((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))

#define PDMA0_QMAN_ENABLE	\
	((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))

#define PDMA1_QMAN_ENABLE	\
	((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
	(0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
	(0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))

/* QM_IDLE_MASK is valid for all engines QM idle check */
#define QM_IDLE_MASK	(DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
			DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \
			DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK)

#define QM_ARC_IDLE_MASK	DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK

#define MME_ARCH_IDLE_MASK	\
			(DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \
			DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \
			DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \
			DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \
			DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \
			DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK)

#define TPC_IDLE_MASK	(DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \
			DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \
			DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \
			DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \
			DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK)

#define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100

#define DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK 0x40

/* CGM_IDLE_MASK is valid for all engines CGM idle check */
#define CGM_IDLE_MASK	DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK

#define QM_GLBL_CFG1_PQF_STOP		PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK
#define QM_GLBL_CFG1_CQF_STOP		PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK
#define QM_GLBL_CFG1_CP_STOP		PDMA0_QM_GLBL_CFG1_CP_STOP_MASK
#define QM_GLBL_CFG1_PQF_FLUSH		PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK

Annotation

Implementation Notes