drivers/accel/habanalabs/gaudi2/gaudi2_security.c

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/gaudi2/gaudi2_security.c

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/gaudi2/gaudi2_security.c
Extension
.c
Size
142084 bytes
Lines
3874
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rr_config {
	u64 min;
	u64 max;
	u32 index;
	u8 type;
};

struct gaudi2_atypical_bp_blocks {
	u32 mm_block_base_addr;
	u32 block_size;
	u32 glbl_sec_offset;
	u32 glbl_sec_length;
};

static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
	mmDCORE0_SYNC_MNGR_OBJS_BASE,
	128 * 1024,
	SM_OBJS_PROT_BITS_OFFS,
	640
};

static const u32 gaudi2_pb_sft0[] = {
	mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
	mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
	mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
	mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
	mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
	mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
	mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
	mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
	mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
	mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
	mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
	mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
	mmSFT0_BASE,
};

static const u32 gaudi2_pb_dcr0_hif[] = {
	mmDCORE0_HIF0_BASE,
};

static const u32 gaudi2_pb_dcr0_rtr0[] = {
	mmDCORE0_RTR0_CTRL_BASE,
	mmDCORE0_RTR0_H3_BASE,
	mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
	mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
	mmDCORE0_RTR0_BASE,
	mmDCORE0_RTR0_DBG_ADDR_BASE,
};

static const u32 gaudi2_pb_dcr0_hmmu0[] = {
	mmDCORE0_HMMU0_MMU_BASE,
	mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
	mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
	mmDCORE0_HMMU0_STLB_BASE,
};

static const u32 gaudi2_pb_cpu_if[] = {
	mmCPU_IF_BASE,
};

static const u32 gaudi2_pb_cpu[] = {
	mmCPU_CA53_CFG_BASE,
	mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_kdma[] = {
	mmARC_FARM_KDMA_BASE,
	mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
};

static const u32 gaudi2_pb_pdma0[] = {
	mmPDMA0_CORE_BASE,
	mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
	mmPDMA0_QM_BASE,
};

static const u32 gaudi2_pb_pdma0_arc[] = {
	mmPDMA0_QM_ARC_AUX_BASE,
};

static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
	{mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
	{mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
	{mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
	{mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
	{mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
	{mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
	{mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
	{mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},

Annotation

Implementation Notes