drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h

Extension

.h

Size

35070 bytes

Lines

897

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_
#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_

/*
 *****************************************
 *   DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL                               0x4C1108

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0                          0x4C1114

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1                          0x4C1118

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2                          0x4C111C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3                          0x4C1120

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4                          0x4C1124

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5                          0x4C1128

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6                          0x4C112C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7                          0x4C1130

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8                          0x4C1134

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9                          0x4C1138

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10                         0x4C113C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11                         0x4C1140

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12                         0x4C1144

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13                         0x4C1148

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14                         0x4C114C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15                         0x4C1150

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16                         0x4C1154

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17                         0x4C1158

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18                         0x4C115C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19                         0x4C1160

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20                         0x4C1164

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21                         0x4C1168

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22                         0x4C116C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23                         0x4C1170

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24                         0x4C1174

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25                         0x4C1178

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26                         0x4C117C

#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27                         0x4C1180

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0                         0x4C1184

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1                         0x4C1188

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2                         0x4C118C

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3                         0x4C1190

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4                         0x4C1194

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5                         0x4C1198

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6                         0x4C119C

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7                         0x4C11A0

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8                         0x4C11A4

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9                         0x4C11A8

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10                        0x4C11AC

#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11                        0x4C11B0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.