drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h
Extension: .h
Size: 35070 bytes
Lines: 897
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_
#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_

/*
 *****************************************
 *   DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL                               0x481108

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0                          0x481114

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1                          0x481118

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2                          0x48111C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3                          0x481120

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4                          0x481124

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5                          0x481128

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6                          0x48112C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7                          0x481130

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8                          0x481134

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9                          0x481138

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10                         0x48113C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11                         0x481140

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12                         0x481144

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13                         0x481148

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14                         0x48114C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15                         0x481150

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16                         0x481154

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17                         0x481158

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18                         0x48115C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19                         0x481160

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20                         0x481164

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21                         0x481168

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22                         0x48116C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23                         0x481170

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24                         0x481174

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25                         0x481178

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26                         0x48117C

#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27                         0x481180

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0                         0x481184

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1                         0x481188

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2                         0x48118C

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3                         0x481190

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4                         0x481194

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5                         0x481198

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6                         0x48119C

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7                         0x4811A0

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8                         0x4811A4

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9                         0x4811A8

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10                        0x4811AC

#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11                        0x4811B0

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.