drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h
Extension
.h
Size
35070 bytes
Lines
897
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_
#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_

/*
 *****************************************
 *   DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL                               0x482108

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0                          0x482114

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1                          0x482118

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2                          0x48211C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3                          0x482120

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4                          0x482124

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5                          0x482128

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6                          0x48212C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7                          0x482130

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8                          0x482134

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9                          0x482138

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10                         0x48213C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11                         0x482140

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12                         0x482144

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13                         0x482148

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14                         0x48214C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15                         0x482150

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16                         0x482154

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17                         0x482158

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18                         0x48215C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19                         0x482160

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20                         0x482164

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21                         0x482168

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22                         0x48216C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23                         0x482170

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24                         0x482174

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25                         0x482178

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26                         0x48217C

#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27                         0x482180

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0                         0x482184

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1                         0x482188

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2                         0x48218C

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3                         0x482190

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4                         0x482194

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5                         0x482198

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6                         0x48219C

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7                         0x4821A0

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8                         0x4821A4

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9                         0x4821A8

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10                        0x4821AC

#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11                        0x4821B0

Annotation

Implementation Notes