drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h

Extension

.h

Size

16724 bytes

Lines

349

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA0_CORE_MASKS_H_
#define ASIC_REG_DMA0_CORE_MASKS_H_

/*
 *****************************************
 *   DMA0_CORE (Prototype: DMA_CORE)
 *****************************************
 */

/* DMA0_CORE_CFG_0 */
#define DMA0_CORE_CFG_0_EN_SHIFT                                     0
#define DMA0_CORE_CFG_0_EN_MASK                                      0x1

/* DMA0_CORE_CFG_1 */
#define DMA0_CORE_CFG_1_HALT_SHIFT                                   0
#define DMA0_CORE_CFG_1_HALT_MASK                                    0x1
#define DMA0_CORE_CFG_1_FLUSH_SHIFT                                  1
#define DMA0_CORE_CFG_1_FLUSH_MASK                                   0x2
#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT                          2
#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK                           0x4

/* DMA0_CORE_LBW_MAX_OUTSTAND */
#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT                         0
#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK                          0x1F

/* DMA0_CORE_SRC_BASE_LO */
#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT                              0
#define DMA0_CORE_SRC_BASE_LO_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_SRC_BASE_HI */
#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT                              0
#define DMA0_CORE_SRC_BASE_HI_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_DST_BASE_LO */
#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT                              0
#define DMA0_CORE_DST_BASE_LO_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_DST_BASE_HI */
#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT                              0
#define DMA0_CORE_DST_BASE_HI_VAL_MASK                               0xFFFFFF
#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT                        24
#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK                         0xFF000000

/* DMA0_CORE_SRC_TSIZE_1 */
#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT                              0
#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_SRC_STRIDE_1 */
#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT                             0
#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK                              0xFFFFFFFF

/* DMA0_CORE_SRC_TSIZE_2 */
#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT                              0
#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_SRC_STRIDE_2 */
#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT                             0
#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK                              0xFFFFFFFF

/* DMA0_CORE_SRC_TSIZE_3 */
#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT                              0
#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_SRC_STRIDE_3 */
#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT                             0
#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK                              0xFFFFFFFF

/* DMA0_CORE_SRC_TSIZE_4 */
#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT                              0
#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_SRC_STRIDE_4 */
#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT                             0
#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK                              0xFFFFFFFF

/* DMA0_CORE_SRC_TSIZE_0 */
#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT                              0
#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_DST_TSIZE_1 */
#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT                              0
#define DMA0_CORE_DST_TSIZE_1_VAL_MASK                               0xFFFFFFFF

/* DMA0_CORE_DST_STRIDE_1 */
#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT                             0
#define DMA0_CORE_DST_STRIDE_1_VAL_MASK                              0xFFFFFFFF

/* DMA0_CORE_DST_TSIZE_2 */
#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT                              0
#define DMA0_CORE_DST_TSIZE_2_VAL_MASK                               0xFFFFFFFF

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.