drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h

Extension

.h

Size

5800 bytes

Lines

157

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA0_CORE_REGS_H_
#define ASIC_REG_DMA0_CORE_REGS_H_

/*
 *****************************************
 *   DMA0_CORE (Prototype: DMA_CORE)
 *****************************************
 */

#define mmDMA0_CORE_CFG_0                                            0x500000

#define mmDMA0_CORE_CFG_1                                            0x500004

#define mmDMA0_CORE_LBW_MAX_OUTSTAND                                 0x500008

#define mmDMA0_CORE_SRC_BASE_LO                                      0x500014

#define mmDMA0_CORE_SRC_BASE_HI                                      0x500018

#define mmDMA0_CORE_DST_BASE_LO                                      0x50001C

#define mmDMA0_CORE_DST_BASE_HI                                      0x500020

#define mmDMA0_CORE_SRC_TSIZE_1                                      0x50002C

#define mmDMA0_CORE_SRC_STRIDE_1                                     0x500030

#define mmDMA0_CORE_SRC_TSIZE_2                                      0x500034

#define mmDMA0_CORE_SRC_STRIDE_2                                     0x500038

#define mmDMA0_CORE_SRC_TSIZE_3                                      0x50003C

#define mmDMA0_CORE_SRC_STRIDE_3                                     0x500040

#define mmDMA0_CORE_SRC_TSIZE_4                                      0x500044

#define mmDMA0_CORE_SRC_STRIDE_4                                     0x500048

#define mmDMA0_CORE_SRC_TSIZE_0                                      0x50004C

#define mmDMA0_CORE_DST_TSIZE_1                                      0x500054

#define mmDMA0_CORE_DST_STRIDE_1                                     0x500058

#define mmDMA0_CORE_DST_TSIZE_2                                      0x50005C

#define mmDMA0_CORE_DST_STRIDE_2                                     0x500060

#define mmDMA0_CORE_DST_TSIZE_3                                      0x500064

#define mmDMA0_CORE_DST_STRIDE_3                                     0x500068

#define mmDMA0_CORE_DST_TSIZE_4                                      0x50006C

#define mmDMA0_CORE_DST_STRIDE_4                                     0x500070

#define mmDMA0_CORE_DST_TSIZE_0                                      0x500074

#define mmDMA0_CORE_COMMIT                                           0x500078

#define mmDMA0_CORE_WR_COMP_WDATA                                    0x50007C

#define mmDMA0_CORE_WR_COMP_ADDR_LO                                  0x500080

#define mmDMA0_CORE_WR_COMP_ADDR_HI                                  0x500084

#define mmDMA0_CORE_WR_COMP_AWUSER_31_11                             0x500088

#define mmDMA0_CORE_TE_NUMROWS                                       0x500094

#define mmDMA0_CORE_PROT                                             0x5000B8

#define mmDMA0_CORE_SECURE_PROPS                                     0x5000F0

#define mmDMA0_CORE_NON_SECURE_PROPS                                 0x5000F4

#define mmDMA0_CORE_RD_MAX_OUTSTAND                                  0x500100

#define mmDMA0_CORE_RD_MAX_SIZE                                      0x500104

#define mmDMA0_CORE_RD_ARCACHE                                       0x500108

#define mmDMA0_CORE_RD_ARUSER_31_11                                  0x500110

#define mmDMA0_CORE_RD_INFLIGHTS                                     0x500114

#define mmDMA0_CORE_WR_MAX_OUTSTAND                                  0x500120

#define mmDMA0_CORE_WR_MAX_AWID                                      0x500124

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.