drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h

Extension

.h

Size

32569 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA1_QM_REGS_H_
#define ASIC_REG_DMA1_QM_REGS_H_

/*
 *****************************************
 *   DMA1_QM (Prototype: QMAN)
 *****************************************
 */

#define mmDMA1_QM_GLBL_CFG0                                          0x528000

#define mmDMA1_QM_GLBL_CFG1                                          0x528004

#define mmDMA1_QM_GLBL_PROT                                          0x528008

#define mmDMA1_QM_GLBL_ERR_CFG                                       0x52800C

#define mmDMA1_QM_GLBL_SECURE_PROPS_0                                0x528010

#define mmDMA1_QM_GLBL_SECURE_PROPS_1                                0x528014

#define mmDMA1_QM_GLBL_SECURE_PROPS_2                                0x528018

#define mmDMA1_QM_GLBL_SECURE_PROPS_3                                0x52801C

#define mmDMA1_QM_GLBL_SECURE_PROPS_4                                0x528020

#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0                            0x528024

#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1                            0x528028

#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2                            0x52802C

#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3                            0x528030

#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4                            0x528034

#define mmDMA1_QM_GLBL_STS0                                          0x528038

#define mmDMA1_QM_GLBL_STS1_0                                        0x528040

#define mmDMA1_QM_GLBL_STS1_1                                        0x528044

#define mmDMA1_QM_GLBL_STS1_2                                        0x528048

#define mmDMA1_QM_GLBL_STS1_3                                        0x52804C

#define mmDMA1_QM_GLBL_STS1_4                                        0x528050

#define mmDMA1_QM_GLBL_MSG_EN_0                                      0x528054

#define mmDMA1_QM_GLBL_MSG_EN_1                                      0x528058

#define mmDMA1_QM_GLBL_MSG_EN_2                                      0x52805C

#define mmDMA1_QM_GLBL_MSG_EN_3                                      0x528060

#define mmDMA1_QM_GLBL_MSG_EN_4                                      0x528068

#define mmDMA1_QM_PQ_BASE_LO_0                                       0x528070

#define mmDMA1_QM_PQ_BASE_LO_1                                       0x528074

#define mmDMA1_QM_PQ_BASE_LO_2                                       0x528078

#define mmDMA1_QM_PQ_BASE_LO_3                                       0x52807C

#define mmDMA1_QM_PQ_BASE_HI_0                                       0x528080

#define mmDMA1_QM_PQ_BASE_HI_1                                       0x528084

#define mmDMA1_QM_PQ_BASE_HI_2                                       0x528088

#define mmDMA1_QM_PQ_BASE_HI_3                                       0x52808C

#define mmDMA1_QM_PQ_SIZE_0                                          0x528090

#define mmDMA1_QM_PQ_SIZE_1                                          0x528094

#define mmDMA1_QM_PQ_SIZE_2                                          0x528098

#define mmDMA1_QM_PQ_SIZE_3                                          0x52809C

#define mmDMA1_QM_PQ_PI_0                                            0x5280A0

#define mmDMA1_QM_PQ_PI_1                                            0x5280A4

#define mmDMA1_QM_PQ_PI_2                                            0x5280A8

#define mmDMA1_QM_PQ_PI_3                                            0x5280AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.