drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h

Extension

.h

Size

5800 bytes

Lines

157

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA5_CORE_REGS_H_
#define ASIC_REG_DMA5_CORE_REGS_H_

/*
 *****************************************
 *   DMA5_CORE (Prototype: DMA_CORE)
 *****************************************
 */

#define mmDMA5_CORE_CFG_0                                            0x5A0000

#define mmDMA5_CORE_CFG_1                                            0x5A0004

#define mmDMA5_CORE_LBW_MAX_OUTSTAND                                 0x5A0008

#define mmDMA5_CORE_SRC_BASE_LO                                      0x5A0014

#define mmDMA5_CORE_SRC_BASE_HI                                      0x5A0018

#define mmDMA5_CORE_DST_BASE_LO                                      0x5A001C

#define mmDMA5_CORE_DST_BASE_HI                                      0x5A0020

#define mmDMA5_CORE_SRC_TSIZE_1                                      0x5A002C

#define mmDMA5_CORE_SRC_STRIDE_1                                     0x5A0030

#define mmDMA5_CORE_SRC_TSIZE_2                                      0x5A0034

#define mmDMA5_CORE_SRC_STRIDE_2                                     0x5A0038

#define mmDMA5_CORE_SRC_TSIZE_3                                      0x5A003C

#define mmDMA5_CORE_SRC_STRIDE_3                                     0x5A0040

#define mmDMA5_CORE_SRC_TSIZE_4                                      0x5A0044

#define mmDMA5_CORE_SRC_STRIDE_4                                     0x5A0048

#define mmDMA5_CORE_SRC_TSIZE_0                                      0x5A004C

#define mmDMA5_CORE_DST_TSIZE_1                                      0x5A0054

#define mmDMA5_CORE_DST_STRIDE_1                                     0x5A0058

#define mmDMA5_CORE_DST_TSIZE_2                                      0x5A005C

#define mmDMA5_CORE_DST_STRIDE_2                                     0x5A0060

#define mmDMA5_CORE_DST_TSIZE_3                                      0x5A0064

#define mmDMA5_CORE_DST_STRIDE_3                                     0x5A0068

#define mmDMA5_CORE_DST_TSIZE_4                                      0x5A006C

#define mmDMA5_CORE_DST_STRIDE_4                                     0x5A0070

#define mmDMA5_CORE_DST_TSIZE_0                                      0x5A0074

#define mmDMA5_CORE_COMMIT                                           0x5A0078

#define mmDMA5_CORE_WR_COMP_WDATA                                    0x5A007C

#define mmDMA5_CORE_WR_COMP_ADDR_LO                                  0x5A0080

#define mmDMA5_CORE_WR_COMP_ADDR_HI                                  0x5A0084

#define mmDMA5_CORE_WR_COMP_AWUSER_31_11                             0x5A0088

#define mmDMA5_CORE_TE_NUMROWS                                       0x5A0094

#define mmDMA5_CORE_PROT                                             0x5A00B8

#define mmDMA5_CORE_SECURE_PROPS                                     0x5A00F0

#define mmDMA5_CORE_NON_SECURE_PROPS                                 0x5A00F4

#define mmDMA5_CORE_RD_MAX_OUTSTAND                                  0x5A0100

#define mmDMA5_CORE_RD_MAX_SIZE                                      0x5A0104

#define mmDMA5_CORE_RD_ARCACHE                                       0x5A0108

#define mmDMA5_CORE_RD_ARUSER_31_11                                  0x5A0110

#define mmDMA5_CORE_RD_INFLIGHTS                                     0x5A0114

#define mmDMA5_CORE_WR_MAX_OUTSTAND                                  0x5A0120

#define mmDMA5_CORE_WR_MAX_AWID                                      0x5A0124

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.