drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h

Extension

.h

Size

32569 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA5_QM_REGS_H_
#define ASIC_REG_DMA5_QM_REGS_H_

/*
 *****************************************
 *   DMA5_QM (Prototype: QMAN)
 *****************************************
 */

#define mmDMA5_QM_GLBL_CFG0                                          0x5A8000

#define mmDMA5_QM_GLBL_CFG1                                          0x5A8004

#define mmDMA5_QM_GLBL_PROT                                          0x5A8008

#define mmDMA5_QM_GLBL_ERR_CFG                                       0x5A800C

#define mmDMA5_QM_GLBL_SECURE_PROPS_0                                0x5A8010

#define mmDMA5_QM_GLBL_SECURE_PROPS_1                                0x5A8014

#define mmDMA5_QM_GLBL_SECURE_PROPS_2                                0x5A8018

#define mmDMA5_QM_GLBL_SECURE_PROPS_3                                0x5A801C

#define mmDMA5_QM_GLBL_SECURE_PROPS_4                                0x5A8020

#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0                            0x5A8024

#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1                            0x5A8028

#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2                            0x5A802C

#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3                            0x5A8030

#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4                            0x5A8034

#define mmDMA5_QM_GLBL_STS0                                          0x5A8038

#define mmDMA5_QM_GLBL_STS1_0                                        0x5A8040

#define mmDMA5_QM_GLBL_STS1_1                                        0x5A8044

#define mmDMA5_QM_GLBL_STS1_2                                        0x5A8048

#define mmDMA5_QM_GLBL_STS1_3                                        0x5A804C

#define mmDMA5_QM_GLBL_STS1_4                                        0x5A8050

#define mmDMA5_QM_GLBL_MSG_EN_0                                      0x5A8054

#define mmDMA5_QM_GLBL_MSG_EN_1                                      0x5A8058

#define mmDMA5_QM_GLBL_MSG_EN_2                                      0x5A805C

#define mmDMA5_QM_GLBL_MSG_EN_3                                      0x5A8060

#define mmDMA5_QM_GLBL_MSG_EN_4                                      0x5A8068

#define mmDMA5_QM_PQ_BASE_LO_0                                       0x5A8070

#define mmDMA5_QM_PQ_BASE_LO_1                                       0x5A8074

#define mmDMA5_QM_PQ_BASE_LO_2                                       0x5A8078

#define mmDMA5_QM_PQ_BASE_LO_3                                       0x5A807C

#define mmDMA5_QM_PQ_BASE_HI_0                                       0x5A8080

#define mmDMA5_QM_PQ_BASE_HI_1                                       0x5A8084

#define mmDMA5_QM_PQ_BASE_HI_2                                       0x5A8088

#define mmDMA5_QM_PQ_BASE_HI_3                                       0x5A808C

#define mmDMA5_QM_PQ_SIZE_0                                          0x5A8090

#define mmDMA5_QM_PQ_SIZE_1                                          0x5A8094

#define mmDMA5_QM_PQ_SIZE_2                                          0x5A8098

#define mmDMA5_QM_PQ_SIZE_3                                          0x5A809C

#define mmDMA5_QM_PQ_PI_0                                            0x5A80A0

#define mmDMA5_QM_PQ_PI_1                                            0x5A80A4

#define mmDMA5_QM_PQ_PI_2                                            0x5A80A8

#define mmDMA5_QM_PQ_PI_3                                            0x5A80AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.