drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h

Extension

.h

Size

32569 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DMA7_QM_REGS_H_
#define ASIC_REG_DMA7_QM_REGS_H_

/*
 *****************************************
 *   DMA7_QM (Prototype: QMAN)
 *****************************************
 */

#define mmDMA7_QM_GLBL_CFG0                                          0x5E8000

#define mmDMA7_QM_GLBL_CFG1                                          0x5E8004

#define mmDMA7_QM_GLBL_PROT                                          0x5E8008

#define mmDMA7_QM_GLBL_ERR_CFG                                       0x5E800C

#define mmDMA7_QM_GLBL_SECURE_PROPS_0                                0x5E8010

#define mmDMA7_QM_GLBL_SECURE_PROPS_1                                0x5E8014

#define mmDMA7_QM_GLBL_SECURE_PROPS_2                                0x5E8018

#define mmDMA7_QM_GLBL_SECURE_PROPS_3                                0x5E801C

#define mmDMA7_QM_GLBL_SECURE_PROPS_4                                0x5E8020

#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0                            0x5E8024

#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1                            0x5E8028

#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2                            0x5E802C

#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3                            0x5E8030

#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4                            0x5E8034

#define mmDMA7_QM_GLBL_STS0                                          0x5E8038

#define mmDMA7_QM_GLBL_STS1_0                                        0x5E8040

#define mmDMA7_QM_GLBL_STS1_1                                        0x5E8044

#define mmDMA7_QM_GLBL_STS1_2                                        0x5E8048

#define mmDMA7_QM_GLBL_STS1_3                                        0x5E804C

#define mmDMA7_QM_GLBL_STS1_4                                        0x5E8050

#define mmDMA7_QM_GLBL_MSG_EN_0                                      0x5E8054

#define mmDMA7_QM_GLBL_MSG_EN_1                                      0x5E8058

#define mmDMA7_QM_GLBL_MSG_EN_2                                      0x5E805C

#define mmDMA7_QM_GLBL_MSG_EN_3                                      0x5E8060

#define mmDMA7_QM_GLBL_MSG_EN_4                                      0x5E8068

#define mmDMA7_QM_PQ_BASE_LO_0                                       0x5E8070

#define mmDMA7_QM_PQ_BASE_LO_1                                       0x5E8074

#define mmDMA7_QM_PQ_BASE_LO_2                                       0x5E8078

#define mmDMA7_QM_PQ_BASE_LO_3                                       0x5E807C

#define mmDMA7_QM_PQ_BASE_HI_0                                       0x5E8080

#define mmDMA7_QM_PQ_BASE_HI_1                                       0x5E8084

#define mmDMA7_QM_PQ_BASE_HI_2                                       0x5E8088

#define mmDMA7_QM_PQ_BASE_HI_3                                       0x5E808C

#define mmDMA7_QM_PQ_SIZE_0                                          0x5E8090

#define mmDMA7_QM_PQ_SIZE_1                                          0x5E8094

#define mmDMA7_QM_PQ_SIZE_2                                          0x5E8098

#define mmDMA7_QM_PQ_SIZE_3                                          0x5E809C

#define mmDMA7_QM_PQ_PI_0                                            0x5E80A0

#define mmDMA7_QM_PQ_PI_1                                            0x5E80A4

#define mmDMA7_QM_PQ_PI_2                                            0x5E80A8

#define mmDMA7_QM_PQ_PI_3                                            0x5E80AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.