drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h

File Facts

System: Linux kernel
Corpus path: drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h
Extension: .h
Size: 303071 bytes
Lines: 4975
Domain: Driver Families
Bucket: drivers/accel
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef GAUDI_BLOCKS_H_
#define GAUDI_BLOCKS_H_

#define mmNIC0_PHY0_BASE                           0x0ull
#define NIC0_PHY0_MAX_OFFSET                       0x9F13
#define mmMME0_ACC_BASE                            0x7FFC020000ull
#define MME0_ACC_MAX_OFFSET                        0x5C00
#define MME0_ACC_SECTION                           0x20000
#define mmMME0_SBAB_BASE                           0x7FFC040000ull
#define MME0_SBAB_MAX_OFFSET                       0x5800
#define MME0_SBAB_SECTION                          0x1000
#define mmMME0_PRTN_BASE                           0x7FFC041000ull
#define MME0_PRTN_MAX_OFFSET                       0x5000
#define MME0_PRTN_SECTION                          0x1F000
#define mmMME0_CTRL_BASE                           0x7FFC060000ull
#define MME0_CTRL_MAX_OFFSET                       0xDA80
#define MME0_CTRL_SECTION                          0x8000
#define mmARCH_MME0_CTRL_BASE                      0x7FFC060008ull
#define ARCH_MME0_CTRL_MAX_OFFSET                  0x3400
#define ARCH_MME0_CTRL_SECTION                     0x3400
#define mmARCH_TENSOR_S_MME0_CTRL_BASE             0x7FFC06003Cull
#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET         0x4C00
#define ARCH_TENSOR_S_MME0_CTRL_SECTION            0x4C00
#define mmARCH_AGU_S_MME0_CTRL_BASE                0x7FFC060088ull
#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET            0x2400
#define ARCH_AGU_S_MME0_CTRL_SECTION               0x2400
#define mmARCH_TENSOR_L_MME0_CTRL_BASE             0x7FFC0600ACull
#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET         0x4C00
#define ARCH_TENSOR_L_MME0_CTRL_SECTION            0x4C00
#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE          0x7FFC0600F8ull
#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET      0x2400
#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION         0x2400
#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE         0x7FFC06011Cull
#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET     0x2400
#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION        0x2400
#define mmARCH_TENSOR_O_MME0_CTRL_BASE             0x7FFC060140ull
#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET         0x4C00
#define ARCH_TENSOR_O_MME0_CTRL_SECTION            0x4C00
#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE          0x7FFC06018Cull
#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET      0x2400
#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION         0x2400
#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE         0x7FFC0601B0ull
#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET     0x2400
#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION        0x2400
#define mmARCH_DESC_MME0_CTRL_BASE                 0x7FFC0601D4ull
#define ARCH_DESC_MME0_CTRL_MAX_OFFSET             0x5400
#define ARCH_DESC_MME0_CTRL_SECTION                0x2340
#define mmSHADOW_0_MME0_CTRL_BASE                  0x7FFC060408ull
#define SHADOW_0_MME0_CTRL_MAX_OFFSET              0x3400
#define SHADOW_0_MME0_CTRL_SECTION                 0x3400
#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE         0x7FFC06043Cull
#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION        0x4C00
#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE            0x7FFC060488ull
#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
#define SHADOW_0_AGU_S_MME0_CTRL_SECTION           0x2400
#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE         0x7FFC0604ACull
#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION        0x4C00
#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC0604F8ull
#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION     0x2400
#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE     0x7FFC06051Cull
#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION    0x2400
#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE         0x7FFC060540ull
#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET     0x4C00
#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION        0x4C00
#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE      0x7FFC06058Cull
#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET  0x2400
#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION     0x2400
#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE     0x7FFC0605B0ull
#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION    0x2400
#define mmSHADOW_0_DESC_MME0_CTRL_BASE             0x7FFC0605D4ull
#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET         0x5400
#define SHADOW_0_DESC_MME0_CTRL_SECTION            0xB400
#define mmSHADOW_1_MME0_CTRL_BASE                  0x7FFC060688ull
#define SHADOW_1_MME0_CTRL_MAX_OFFSET              0x3400
#define SHADOW_1_MME0_CTRL_SECTION                 0x3400
#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE         0x7FFC0606BCull
#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET     0x4C00
#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION        0x4C00
#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE            0x7FFC060708ull
#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET        0x2400
#define SHADOW_1_AGU_S_MME0_CTRL_SECTION           0x2400
#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE         0x7FFC06072Cull
#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET     0x4C00
#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION        0x4C00
#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE      0x7FFC060778ull

Annotation

Atlas domain: Driver Families / drivers/accel.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.