drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h- Extension
.h- Size
- 56428 bytes
- Lines
- 1457
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_MME0_CTRL_REGS_H_
#define ASIC_REG_MME0_CTRL_REGS_H_
/*
*****************************************
* MME0_CTRL (Prototype: MME)
*****************************************
*/
#define mmMME0_CTRL_ARCH_STATUS 0x60000
#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008
#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C
#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010
#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014
#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018
#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C
#define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020
#define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024
#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028
#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x6002C
#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x60030
#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x60034
#define mmMME0_CTRL_ARCH_OUTER_LOOP 0x60038
#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x6003C
#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x60040
#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x60044
#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x60048
#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x6004C
#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x60050
#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x60054
#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x60058
#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x6005C
#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x60060
#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x60064
#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x60068
#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x6006C
#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x60070
#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x60074
#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x60078
#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x6007C
#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x60080
#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60084
#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x60088
#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x6008C
#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x60090
#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x60094
#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x60098
#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0 0x6009C
#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1 0x600A0
#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2 0x600A4
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.