drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_masks.h- Extension
.h- Size
- 43687 bytes
- Lines
- 801
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_NIC0_QM0_MASKS_H_
#define ASIC_REG_NIC0_QM0_MASKS_H_
/*
*****************************************
* NIC0_QM0 (Prototype: QMAN)
*****************************************
*/
/* NIC0_QM0_GLBL_CFG0 */
#define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
#define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
#define NIC0_QM0_GLBL_CFG0_CQF_EN_SHIFT 4
#define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
#define NIC0_QM0_GLBL_CFG0_CP_EN_SHIFT 9
#define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
/* NIC0_QM0_GLBL_CFG1 */
#define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
#define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
#define NIC0_QM0_GLBL_CFG1_CQF_STOP_SHIFT 4
#define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
#define NIC0_QM0_GLBL_CFG1_CP_STOP_SHIFT 9
#define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_SHIFT 16
#define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_SHIFT 20
#define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_SHIFT 25
#define NIC0_QM0_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000
/* NIC0_QM0_GLBL_PROT */
#define NIC0_QM0_GLBL_PROT_PQF_SHIFT 0
#define NIC0_QM0_GLBL_PROT_PQF_MASK 0xF
#define NIC0_QM0_GLBL_PROT_CQF_SHIFT 4
#define NIC0_QM0_GLBL_PROT_CQF_MASK 0x1F0
#define NIC0_QM0_GLBL_PROT_CP_SHIFT 9
#define NIC0_QM0_GLBL_PROT_CP_MASK 0x3E00
#define NIC0_QM0_GLBL_PROT_ERR_SHIFT 14
#define NIC0_QM0_GLBL_PROT_ERR_MASK 0x4000
#define NIC0_QM0_GLBL_PROT_ARB_SHIFT 15
#define NIC0_QM0_GLBL_PROT_ARB_MASK 0x8000
/* NIC0_QM0_GLBL_ERR_CFG */
#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0
#define NIC0_QM0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF
#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4
#define NIC0_QM0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0
#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9
#define NIC0_QM0_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00
#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16
#define NIC0_QM0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000
#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20
#define NIC0_QM0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000
#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25
#define NIC0_QM0_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000
#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31
#define NIC0_QM0_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000
/* NIC0_QM0_GLBL_SECURE_PROPS */
#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_SHIFT 0
#define NIC0_QM0_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_SHIFT 0
#define NIC0_QM0_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_SHIFT 0
#define NIC0_QM0_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_SHIFT 0
#define NIC0_QM0_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_SHIFT 0
#define NIC0_QM0_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10
#define NIC0_QM0_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400
#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10
#define NIC0_QM0_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400
#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10
#define NIC0_QM0_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400
#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10
#define NIC0_QM0_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400
#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10
#define NIC0_QM0_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400
/* NIC0_QM0_GLBL_NON_SECURE_PROPS */
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0
#define NIC0_QM0_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FFAnnotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.