drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm0_regs.h

Extension

.h

Size

32573 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_NIC0_QM0_REGS_H_
#define ASIC_REG_NIC0_QM0_REGS_H_

/*
 *****************************************
 *   NIC0_QM0 (Prototype: QMAN)
 *****************************************
 */

#define mmNIC0_QM0_GLBL_CFG0                                         0xCE0000

#define mmNIC0_QM0_GLBL_CFG1                                         0xCE0004

#define mmNIC0_QM0_GLBL_PROT                                         0xCE0008

#define mmNIC0_QM0_GLBL_ERR_CFG                                      0xCE000C

#define mmNIC0_QM0_GLBL_SECURE_PROPS_0                               0xCE0010

#define mmNIC0_QM0_GLBL_SECURE_PROPS_1                               0xCE0014

#define mmNIC0_QM0_GLBL_SECURE_PROPS_2                               0xCE0018

#define mmNIC0_QM0_GLBL_SECURE_PROPS_3                               0xCE001C

#define mmNIC0_QM0_GLBL_SECURE_PROPS_4                               0xCE0020

#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_0                           0xCE0024

#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_1                           0xCE0028

#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_2                           0xCE002C

#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_3                           0xCE0030

#define mmNIC0_QM0_GLBL_NON_SECURE_PROPS_4                           0xCE0034

#define mmNIC0_QM0_GLBL_STS0                                         0xCE0038

#define mmNIC0_QM0_GLBL_STS1_0                                       0xCE0040

#define mmNIC0_QM0_GLBL_STS1_1                                       0xCE0044

#define mmNIC0_QM0_GLBL_STS1_2                                       0xCE0048

#define mmNIC0_QM0_GLBL_STS1_3                                       0xCE004C

#define mmNIC0_QM0_GLBL_STS1_4                                       0xCE0050

#define mmNIC0_QM0_GLBL_MSG_EN_0                                     0xCE0054

#define mmNIC0_QM0_GLBL_MSG_EN_1                                     0xCE0058

#define mmNIC0_QM0_GLBL_MSG_EN_2                                     0xCE005C

#define mmNIC0_QM0_GLBL_MSG_EN_3                                     0xCE0060

#define mmNIC0_QM0_GLBL_MSG_EN_4                                     0xCE0068

#define mmNIC0_QM0_PQ_BASE_LO_0                                      0xCE0070

#define mmNIC0_QM0_PQ_BASE_LO_1                                      0xCE0074

#define mmNIC0_QM0_PQ_BASE_LO_2                                      0xCE0078

#define mmNIC0_QM0_PQ_BASE_LO_3                                      0xCE007C

#define mmNIC0_QM0_PQ_BASE_HI_0                                      0xCE0080

#define mmNIC0_QM0_PQ_BASE_HI_1                                      0xCE0084

#define mmNIC0_QM0_PQ_BASE_HI_2                                      0xCE0088

#define mmNIC0_QM0_PQ_BASE_HI_3                                      0xCE008C

#define mmNIC0_QM0_PQ_SIZE_0                                         0xCE0090

#define mmNIC0_QM0_PQ_SIZE_1                                         0xCE0094

#define mmNIC0_QM0_PQ_SIZE_2                                         0xCE0098

#define mmNIC0_QM0_PQ_SIZE_3                                         0xCE009C

#define mmNIC0_QM0_PQ_PI_0                                           0xCE00A0

#define mmNIC0_QM0_PQ_PI_1                                           0xCE00A4

#define mmNIC0_QM0_PQ_PI_2                                           0xCE00A8

#define mmNIC0_QM0_PQ_PI_3                                           0xCE00AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.