drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/nic0_qm1_regs.h

Extension

.h

Size

32573 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_NIC0_QM1_REGS_H_
#define ASIC_REG_NIC0_QM1_REGS_H_

/*
 *****************************************
 *   NIC0_QM1 (Prototype: QMAN)
 *****************************************
 */

#define mmNIC0_QM1_GLBL_CFG0                                         0xCE2000

#define mmNIC0_QM1_GLBL_CFG1                                         0xCE2004

#define mmNIC0_QM1_GLBL_PROT                                         0xCE2008

#define mmNIC0_QM1_GLBL_ERR_CFG                                      0xCE200C

#define mmNIC0_QM1_GLBL_SECURE_PROPS_0                               0xCE2010

#define mmNIC0_QM1_GLBL_SECURE_PROPS_1                               0xCE2014

#define mmNIC0_QM1_GLBL_SECURE_PROPS_2                               0xCE2018

#define mmNIC0_QM1_GLBL_SECURE_PROPS_3                               0xCE201C

#define mmNIC0_QM1_GLBL_SECURE_PROPS_4                               0xCE2020

#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0                           0xCE2024

#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1                           0xCE2028

#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2                           0xCE202C

#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3                           0xCE2030

#define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4                           0xCE2034

#define mmNIC0_QM1_GLBL_STS0                                         0xCE2038

#define mmNIC0_QM1_GLBL_STS1_0                                       0xCE2040

#define mmNIC0_QM1_GLBL_STS1_1                                       0xCE2044

#define mmNIC0_QM1_GLBL_STS1_2                                       0xCE2048

#define mmNIC0_QM1_GLBL_STS1_3                                       0xCE204C

#define mmNIC0_QM1_GLBL_STS1_4                                       0xCE2050

#define mmNIC0_QM1_GLBL_MSG_EN_0                                     0xCE2054

#define mmNIC0_QM1_GLBL_MSG_EN_1                                     0xCE2058

#define mmNIC0_QM1_GLBL_MSG_EN_2                                     0xCE205C

#define mmNIC0_QM1_GLBL_MSG_EN_3                                     0xCE2060

#define mmNIC0_QM1_GLBL_MSG_EN_4                                     0xCE2068

#define mmNIC0_QM1_PQ_BASE_LO_0                                      0xCE2070

#define mmNIC0_QM1_PQ_BASE_LO_1                                      0xCE2074

#define mmNIC0_QM1_PQ_BASE_LO_2                                      0xCE2078

#define mmNIC0_QM1_PQ_BASE_LO_3                                      0xCE207C

#define mmNIC0_QM1_PQ_BASE_HI_0                                      0xCE2080

#define mmNIC0_QM1_PQ_BASE_HI_1                                      0xCE2084

#define mmNIC0_QM1_PQ_BASE_HI_2                                      0xCE2088

#define mmNIC0_QM1_PQ_BASE_HI_3                                      0xCE208C

#define mmNIC0_QM1_PQ_SIZE_0                                         0xCE2090

#define mmNIC0_QM1_PQ_SIZE_1                                         0xCE2094

#define mmNIC0_QM1_PQ_SIZE_2                                         0xCE2098

#define mmNIC0_QM1_PQ_SIZE_3                                         0xCE209C

#define mmNIC0_QM1_PQ_PI_0                                           0xCE20A0

#define mmNIC0_QM1_PQ_PI_1                                           0xCE20A4

#define mmNIC0_QM1_PQ_PI_2                                           0xCE20A8

#define mmNIC0_QM1_PQ_PI_3                                           0xCE20AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.