drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/nic2_qm1_regs.h

Extension

.h

Size

32573 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_NIC2_QM1_REGS_H_
#define ASIC_REG_NIC2_QM1_REGS_H_

/*
 *****************************************
 *   NIC2_QM1 (Prototype: QMAN)
 *****************************************
 */

#define mmNIC2_QM1_GLBL_CFG0                                         0xD62000

#define mmNIC2_QM1_GLBL_CFG1                                         0xD62004

#define mmNIC2_QM1_GLBL_PROT                                         0xD62008

#define mmNIC2_QM1_GLBL_ERR_CFG                                      0xD6200C

#define mmNIC2_QM1_GLBL_SECURE_PROPS_0                               0xD62010

#define mmNIC2_QM1_GLBL_SECURE_PROPS_1                               0xD62014

#define mmNIC2_QM1_GLBL_SECURE_PROPS_2                               0xD62018

#define mmNIC2_QM1_GLBL_SECURE_PROPS_3                               0xD6201C

#define mmNIC2_QM1_GLBL_SECURE_PROPS_4                               0xD62020

#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_0                           0xD62024

#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_1                           0xD62028

#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_2                           0xD6202C

#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_3                           0xD62030

#define mmNIC2_QM1_GLBL_NON_SECURE_PROPS_4                           0xD62034

#define mmNIC2_QM1_GLBL_STS0                                         0xD62038

#define mmNIC2_QM1_GLBL_STS1_0                                       0xD62040

#define mmNIC2_QM1_GLBL_STS1_1                                       0xD62044

#define mmNIC2_QM1_GLBL_STS1_2                                       0xD62048

#define mmNIC2_QM1_GLBL_STS1_3                                       0xD6204C

#define mmNIC2_QM1_GLBL_STS1_4                                       0xD62050

#define mmNIC2_QM1_GLBL_MSG_EN_0                                     0xD62054

#define mmNIC2_QM1_GLBL_MSG_EN_1                                     0xD62058

#define mmNIC2_QM1_GLBL_MSG_EN_2                                     0xD6205C

#define mmNIC2_QM1_GLBL_MSG_EN_3                                     0xD62060

#define mmNIC2_QM1_GLBL_MSG_EN_4                                     0xD62068

#define mmNIC2_QM1_PQ_BASE_LO_0                                      0xD62070

#define mmNIC2_QM1_PQ_BASE_LO_1                                      0xD62074

#define mmNIC2_QM1_PQ_BASE_LO_2                                      0xD62078

#define mmNIC2_QM1_PQ_BASE_LO_3                                      0xD6207C

#define mmNIC2_QM1_PQ_BASE_HI_0                                      0xD62080

#define mmNIC2_QM1_PQ_BASE_HI_1                                      0xD62084

#define mmNIC2_QM1_PQ_BASE_HI_2                                      0xD62088

#define mmNIC2_QM1_PQ_BASE_HI_3                                      0xD6208C

#define mmNIC2_QM1_PQ_SIZE_0                                         0xD62090

#define mmNIC2_QM1_PQ_SIZE_1                                         0xD62094

#define mmNIC2_QM1_PQ_SIZE_2                                         0xD62098

#define mmNIC2_QM1_PQ_SIZE_3                                         0xD6209C

#define mmNIC2_QM1_PQ_PI_0                                           0xD620A0

#define mmNIC2_QM1_PQ_PI_1                                           0xD620A4

#define mmNIC2_QM1_PQ_PI_2                                           0xD620A8

#define mmNIC2_QM1_PQ_PI_3                                           0xD620AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.