drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h

Extension

.h

Size

35050 bytes

Lines

897

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_
#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_

/*
 *****************************************
 *   NIF_RTR_CTRL_2 (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmNIF_RTR_CTRL_2_PERM_SEL                                    0x3A6108

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0                               0x3A6114

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1                               0x3A6118

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2                               0x3A611C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3                               0x3A6120

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4                               0x3A6124

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5                               0x3A6128

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6                               0x3A612C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7                               0x3A6130

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8                               0x3A6134

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9                               0x3A6138

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10                              0x3A613C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11                              0x3A6140

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12                              0x3A6144

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13                              0x3A6148

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14                              0x3A614C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15                              0x3A6150

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16                              0x3A6154

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17                              0x3A6158

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18                              0x3A615C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19                              0x3A6160

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20                              0x3A6164

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21                              0x3A6168

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22                              0x3A616C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23                              0x3A6170

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24                              0x3A6174

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25                              0x3A6178

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26                              0x3A617C

#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27                              0x3A6180

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0                              0x3A6184

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1                              0x3A6188

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2                              0x3A618C

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3                              0x3A6190

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4                              0x3A6194

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5                              0x3A6198

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6                              0x3A619C

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7                              0x3A61A0

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8                              0x3A61A4

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9                              0x3A61A8

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10                             0x3A61AC

#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11                             0x3A61B0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.