drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h

Extension

.h

Size

35050 bytes

Lines

897

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_
#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_

/*
 *****************************************
 *   SIF_RTR_CTRL_5 (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmSIF_RTR_CTRL_5_PERM_SEL                                    0x356108

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0                               0x356114

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1                               0x356118

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2                               0x35611C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3                               0x356120

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4                               0x356124

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5                               0x356128

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6                               0x35612C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7                               0x356130

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8                               0x356134

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9                               0x356138

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10                              0x35613C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11                              0x356140

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12                              0x356144

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13                              0x356148

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14                              0x35614C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15                              0x356150

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16                              0x356154

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17                              0x356158

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18                              0x35615C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19                              0x356160

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20                              0x356164

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21                              0x356168

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22                              0x35616C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23                              0x356170

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24                              0x356174

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25                              0x356178

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26                              0x35617C

#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27                              0x356180

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0                              0x356184

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1                              0x356188

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2                              0x35618C

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3                              0x356190

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4                              0x356194

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5                              0x356198

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6                              0x35619C

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7                              0x3561A0

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8                              0x3561A4

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9                              0x3561A8

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10                             0x3561AC

#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11                             0x3561B0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.