drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h

Extension

.h

Size

48056 bytes

Lines

1227

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC5_CFG_REGS_H_
#define ASIC_REG_TPC5_CFG_REGS_H_

/*
 *****************************************
 *   TPC5_CFG (Prototype: TPC)
 *****************************************
 */

#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW                     0xF46400

#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH                    0xF46404

#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE                     0xF46408

#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG                     0xF4640C

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE                        0xF46410

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE                      0xF46414

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE                        0xF46418

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE                      0xF4641C

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE                        0xF46420

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE                      0xF46424

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE                        0xF46428

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE                      0xF4642C

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE                        0xF46430

#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE                      0xF46434

#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW                     0xF46438

#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH                    0xF4643C

#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE                     0xF46440

#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG                     0xF46444

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE                        0xF46448

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE                      0xF4644C

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE                        0xF46450

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE                      0xF46454

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE                        0xF46458

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE                      0xF4645C

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE                        0xF46460

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE                      0xF46464

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE                        0xF46468

#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE                      0xF4646C

#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW                     0xF46470

#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH                    0xF46474

#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE                     0xF46478

#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG                     0xF4647C

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE                        0xF46480

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE                      0xF46484

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE                        0xF46488

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE                      0xF4648C

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE                        0xF46490

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE                      0xF46494

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE                        0xF46498

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE                      0xF4649C

#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE                        0xF464A0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.