drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h

Extension

.h

Size

32569 bytes

Lines

835

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_TPC5_QM_REGS_H_
#define ASIC_REG_TPC5_QM_REGS_H_

/*
 *****************************************
 *   TPC5_QM (Prototype: QMAN)
 *****************************************
 */

#define mmTPC5_QM_GLBL_CFG0                                          0xF48000

#define mmTPC5_QM_GLBL_CFG1                                          0xF48004

#define mmTPC5_QM_GLBL_PROT                                          0xF48008

#define mmTPC5_QM_GLBL_ERR_CFG                                       0xF4800C

#define mmTPC5_QM_GLBL_SECURE_PROPS_0                                0xF48010

#define mmTPC5_QM_GLBL_SECURE_PROPS_1                                0xF48014

#define mmTPC5_QM_GLBL_SECURE_PROPS_2                                0xF48018

#define mmTPC5_QM_GLBL_SECURE_PROPS_3                                0xF4801C

#define mmTPC5_QM_GLBL_SECURE_PROPS_4                                0xF48020

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0                            0xF48024

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1                            0xF48028

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2                            0xF4802C

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3                            0xF48030

#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4                            0xF48034

#define mmTPC5_QM_GLBL_STS0                                          0xF48038

#define mmTPC5_QM_GLBL_STS1_0                                        0xF48040

#define mmTPC5_QM_GLBL_STS1_1                                        0xF48044

#define mmTPC5_QM_GLBL_STS1_2                                        0xF48048

#define mmTPC5_QM_GLBL_STS1_3                                        0xF4804C

#define mmTPC5_QM_GLBL_STS1_4                                        0xF48050

#define mmTPC5_QM_GLBL_MSG_EN_0                                      0xF48054

#define mmTPC5_QM_GLBL_MSG_EN_1                                      0xF48058

#define mmTPC5_QM_GLBL_MSG_EN_2                                      0xF4805C

#define mmTPC5_QM_GLBL_MSG_EN_3                                      0xF48060

#define mmTPC5_QM_GLBL_MSG_EN_4                                      0xF48068

#define mmTPC5_QM_PQ_BASE_LO_0                                       0xF48070

#define mmTPC5_QM_PQ_BASE_LO_1                                       0xF48074

#define mmTPC5_QM_PQ_BASE_LO_2                                       0xF48078

#define mmTPC5_QM_PQ_BASE_LO_3                                       0xF4807C

#define mmTPC5_QM_PQ_BASE_HI_0                                       0xF48080

#define mmTPC5_QM_PQ_BASE_HI_1                                       0xF48084

#define mmTPC5_QM_PQ_BASE_HI_2                                       0xF48088

#define mmTPC5_QM_PQ_BASE_HI_3                                       0xF4808C

#define mmTPC5_QM_PQ_SIZE_0                                          0xF48090

#define mmTPC5_QM_PQ_SIZE_1                                          0xF48094

#define mmTPC5_QM_PQ_SIZE_2                                          0xF48098

#define mmTPC5_QM_PQ_SIZE_3                                          0xF4809C

#define mmTPC5_QM_PQ_PI_0                                            0xF480A0

#define mmTPC5_QM_PQ_PI_1                                            0xF480A4

#define mmTPC5_QM_PQ_PI_2                                            0xF480A8

#define mmTPC5_QM_PQ_PI_3                                            0xF480AC

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.