drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h
Extension
.h
Size
42034 bytes
Lines
711
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct gaudi_async_events_ids_map {
	int fc_id;
	int cpu_id;
	int valid;
	char name[64];
};

static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = {
	{ .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" },
	{ .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" },
	{ .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" },
	{ .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" },
	{ .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" },
	{ .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" },
	{ .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" },
	{ .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" },
	{ .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" },
	{ .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" },
	{ .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" },
	{ .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" },
	{ .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" },
	{ .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" },
	{ .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" },
	{ .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" },
	{ .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" },
	{ .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" },
	{ .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" },
	{ .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" },
	{ .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" },
	{ .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" },
	{ .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" },
	{ .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" },
	{ .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" },
	{ .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" },
	{ .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" },
	{ .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" },
	{ .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" },
	{ .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" },
	{ .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" },
	{ .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" },
	{ .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" },
	{ .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" },
	{ .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" },
	{ .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" },
	{ .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" },
	{ .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" },
	{ .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" },
	{ .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" },
	{ .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" },
	{ .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" },
	{ .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" },
	{ .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" },
	{ .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" },
	{ .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" },
	{ .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" },
	{ .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" },
	{ .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" },
	{ .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" },
	{ .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" },
	{ .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" },
	{ .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" },
	{ .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" },
	{ .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" },
	{ .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" },
	{ .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" },
	{ .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" },
	{ .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" },
	{ .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" },
	{ .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" },
	{ .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" },
	{ .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" },
	{ .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" },
	{ .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" },
	{ .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" },
	{ .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" },
	{ .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" },
	{ .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" },
	{ .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" },
	{ .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" },
	{ .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" },
	{ .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" },
	{ .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" },
	{ .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" },
	{ .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" },
	{ .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" },
	{ .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" },
	{ .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" },
	{ .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" },
	{ .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" },
	{ .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" },

Annotation

Implementation Notes