drivers/accel/habanalabs/include/gaudi/gaudi.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi/gaudi.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi/gaudi.h- Extension
.h- Size
- 1307 bytes
- Lines
- 62
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef GAUDI_H
#define GAUDI_H
#define SRAM_BAR_ID 0
#define CFG_BAR_ID 2
#define HBM_BAR_ID 4
#define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
#define CFG_BAR_SIZE 0x8000000ull /* 128MB */
#define CFG_BASE 0x7FFC000000ull
#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
#define SRAM_BASE_ADDR 0x7FF0000000ull
#define SRAM_SIZE 0x1400000 /* 20MB */
#define SPI_FLASH_BASE_ADDR 0x7FF8000000ull
#define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull
#define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */
#define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull
#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
#define DRAM_PHYS_BASE 0x0ull
#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */
#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */
#define GAUDI_MSI_ENTRIES 32
#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */
#define MAX_ASID 2
#define PROT_BITS_OFFS 0xF80
#define MME_NUMBER_OF_MASTER_ENGINES 2
#define MME_NUMBER_OF_SLAVE_ENGINES 2
#define TPC_NUMBER_OF_ENGINES 8
#define DMA_NUMBER_OF_CHANNELS 8
#define NIC_NUMBER_OF_MACROS 5
#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2)
#define NUMBER_OF_IF 8
#define DEVICE_CACHE_LINE_SIZE 128
#endif /* GAUDI_H */
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.