drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
Extension
.h
Size
5790 bytes
Lines
212
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__
#define __GAUDI2_ARC_COMMON_PACKETS_H__

enum {
	CPU_ID_SCHED_ARC0 = 0, /* FARM_ARC0 */
	CPU_ID_SCHED_ARC1 = 1, /* FARM_ARC1 */
	CPU_ID_SCHED_ARC2 = 2, /* FARM_ARC2 */
	CPU_ID_SCHED_ARC3 = 3, /* FARM_ARC3 */
	/* Dcore1 MME Engine ARC instance used as scheduler */
	CPU_ID_SCHED_ARC4 = 4, /* DCORE1_MME0 */
	/* Dcore3 MME Engine ARC instance used as scheduler */
	CPU_ID_SCHED_ARC5 = 5, /* DCORE3_MME0 */

	CPU_ID_TPC_QMAN_ARC0 = 6,   /* DCORE0_TPC0 */
	CPU_ID_TPC_QMAN_ARC1 = 7,   /* DCORE0_TPC1 */
	CPU_ID_TPC_QMAN_ARC2 = 8,   /* DCORE0_TPC2 */
	CPU_ID_TPC_QMAN_ARC3 = 9,   /* DCORE0_TPC3 */
	CPU_ID_TPC_QMAN_ARC4 = 10,  /* DCORE0_TPC4 */
	CPU_ID_TPC_QMAN_ARC5 = 11,  /* DCORE0_TPC5 */
	CPU_ID_TPC_QMAN_ARC6 = 12,  /* DCORE1_TPC0 */
	CPU_ID_TPC_QMAN_ARC7 = 13,  /* DCORE1_TPC1 */
	CPU_ID_TPC_QMAN_ARC8 = 14,  /* DCORE1_TPC2 */
	CPU_ID_TPC_QMAN_ARC9 = 15,  /* DCORE1_TPC3 */
	CPU_ID_TPC_QMAN_ARC10 = 16, /* DCORE1_TPC4 */
	CPU_ID_TPC_QMAN_ARC11 = 17, /* DCORE1_TPC5 */
	CPU_ID_TPC_QMAN_ARC12 = 18, /* DCORE2_TPC0 */
	CPU_ID_TPC_QMAN_ARC13 = 19, /* DCORE2_TPC1 */
	CPU_ID_TPC_QMAN_ARC14 = 20, /* DCORE2_TPC2 */
	CPU_ID_TPC_QMAN_ARC15 = 21, /* DCORE2_TPC3 */
	CPU_ID_TPC_QMAN_ARC16 = 22, /* DCORE2_TPC4 */
	CPU_ID_TPC_QMAN_ARC17 = 23, /* DCORE2_TPC5 */
	CPU_ID_TPC_QMAN_ARC18 = 24, /* DCORE3_TPC0 */
	CPU_ID_TPC_QMAN_ARC19 = 25, /* DCORE3_TPC1 */
	CPU_ID_TPC_QMAN_ARC20 = 26, /* DCORE3_TPC2 */
	CPU_ID_TPC_QMAN_ARC21 = 27, /* DCORE3_TPC3 */
	CPU_ID_TPC_QMAN_ARC22 = 28, /* DCORE3_TPC4 */
	CPU_ID_TPC_QMAN_ARC23 = 29, /* DCORE3_TPC5 */
	CPU_ID_TPC_QMAN_ARC24 = 30, /* DCORE0_TPC6 - Never present */

	CPU_ID_MME_QMAN_ARC0 = 31, /* DCORE0_MME0 */
	CPU_ID_MME_QMAN_ARC1 = 32, /* DCORE2_MME0 */

	CPU_ID_EDMA_QMAN_ARC0 = 33, /* DCORE0_EDMA0 */
	CPU_ID_EDMA_QMAN_ARC1 = 34, /* DCORE0_EDMA1 */
	CPU_ID_EDMA_QMAN_ARC2 = 35, /* DCORE1_EDMA0 */
	CPU_ID_EDMA_QMAN_ARC3 = 36, /* DCORE1_EDMA1 */
	CPU_ID_EDMA_QMAN_ARC4 = 37, /* DCORE2_EDMA0 */
	CPU_ID_EDMA_QMAN_ARC5 = 38, /* DCORE2_EDMA1 */
	CPU_ID_EDMA_QMAN_ARC6 = 39, /* DCORE3_EDMA0 */
	CPU_ID_EDMA_QMAN_ARC7 = 40, /* DCORE3_EDMA1 */

	CPU_ID_PDMA_QMAN_ARC0 = 41, /* DCORE0_PDMA0 */
	CPU_ID_PDMA_QMAN_ARC1 = 42, /* DCORE0_PDMA1 */

	CPU_ID_ROT_QMAN_ARC0 = 43, /* ROT0 */
	CPU_ID_ROT_QMAN_ARC1 = 44, /* ROT1 */

	CPU_ID_NIC_QMAN_ARC0 = 45,  /* NIC0_0 */
	CPU_ID_NIC_QMAN_ARC1 = 46,  /* NIC0_1 */
	CPU_ID_NIC_QMAN_ARC2 = 47,  /* NIC1_0 */
	CPU_ID_NIC_QMAN_ARC3 = 48,  /* NIC1_1 */
	CPU_ID_NIC_QMAN_ARC4 = 49,  /* NIC2_0 */
	CPU_ID_NIC_QMAN_ARC5 = 50,  /* NIC2_1 */
	CPU_ID_NIC_QMAN_ARC6 = 51,  /* NIC3_0 */
	CPU_ID_NIC_QMAN_ARC7 = 52,  /* NIC3_1 */
	CPU_ID_NIC_QMAN_ARC8 = 53,  /* NIC4_0 */
	CPU_ID_NIC_QMAN_ARC9 = 54,  /* NIC4_1 */
	CPU_ID_NIC_QMAN_ARC10 = 55, /* NIC5_0 */
	CPU_ID_NIC_QMAN_ARC11 = 56, /* NIC5_1 */
	CPU_ID_NIC_QMAN_ARC12 = 57, /* NIC6_0 */
	CPU_ID_NIC_QMAN_ARC13 = 58, /* NIC6_1 */
	CPU_ID_NIC_QMAN_ARC14 = 59, /* NIC7_0 */
	CPU_ID_NIC_QMAN_ARC15 = 60, /* NIC7_1 */
	CPU_ID_NIC_QMAN_ARC16 = 61, /* NIC8_0 */
	CPU_ID_NIC_QMAN_ARC17 = 62, /* NIC8_1 */
	CPU_ID_NIC_QMAN_ARC18 = 63, /* NIC9_0 */
	CPU_ID_NIC_QMAN_ARC19 = 64, /* NIC9_1 */
	CPU_ID_NIC_QMAN_ARC20 = 65, /* NIC10_0 */
	CPU_ID_NIC_QMAN_ARC21 = 66, /* NIC10_1 */
	CPU_ID_NIC_QMAN_ARC22 = 67, /* NIC11_0 */
	CPU_ID_NIC_QMAN_ARC23 = 68, /* NIC11_1 */

	CPU_ID_MAX = 69,
	CPU_ID_SCHED_MAX = 6,

	CPU_ID_ALL = 0xFE,
	CPU_ID_INVALID = 0xFF,
};

enum arc_regions_t {

Annotation

Implementation Notes