drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/arc_farm_arc0_aux_masks.h

Extension

.h

Size

35435 bytes

Lines

820

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_
#define ASIC_REG_ARC_FARM_ARC0_AUX_MASKS_H_

/*
 *****************************************
 *   ARC_FARM_ARC0_AUX
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

/* ARC_FARM_ARC0_AUX_RUN_HALT_REQ */
#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_SHIFT 0
#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_RUN_REQ_MASK 0x1
#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_SHIFT 1
#define ARC_FARM_ARC0_AUX_RUN_HALT_REQ_HALT_REQ_MASK 0x2

/* ARC_FARM_ARC0_AUX_RUN_HALT_ACK */
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_SHIFT 0
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK 0x1
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_SHIFT 4
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK 0x10
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_SHIFT 8
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_HALT_R_MASK 0x100
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_SHIFT 12
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_TF_HALT_R_MASK 0x1000
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_SHIFT 16
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_R_MASK 0x10000
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_SHIFT 17
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_SYS_SLEEP_MODE_R_MASK 0xE0000
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_SHIFT 20
#define ARC_FARM_ARC0_AUX_RUN_HALT_ACK_WATCHDOG_RESET_MASK 0x100000

/* ARC_FARM_ARC0_AUX_RST_VEC_ADDR */
#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_RST_VEC_ADDR_VAL_MASK 0x3FFFFF

/* ARC_FARM_ARC0_AUX_DBG_MODE */
#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_SHIFT 0
#define ARC_FARM_ARC0_AUX_DBG_MODE_DBG_PROT_SEL_MASK 0x1
#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_SHIFT 4
#define ARC_FARM_ARC0_AUX_DBG_MODE_DBGEN_MASK 0x10
#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_SHIFT 8
#define ARC_FARM_ARC0_AUX_DBG_MODE_NIDEN_MASK 0x100
#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_SHIFT 12
#define ARC_FARM_ARC0_AUX_DBG_MODE_CASHE_RST_DISABLE_MASK 0x1000
#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_SHIFT 16
#define ARC_FARM_ARC0_AUX_DBG_MODE_DDCM_DMI_PRIORITY_MASK 0x10000

/* ARC_FARM_ARC0_AUX_CLUSTER_NUM */
#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_CLUSTER_NUM_VAL_MASK 0xFF

/* ARC_FARM_ARC0_AUX_ARC_NUM */
#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_ARC_NUM_VAL_MASK 0xFF

/* ARC_FARM_ARC0_AUX_WAKE_UP_EVENT */
#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_WAKE_UP_EVENT_VAL_MASK 0x1

/* ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE */
#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_DCCM_SYS_ADDR_BASE_VAL_MASK 0xFFFFFFFF

/* ARC_FARM_ARC0_AUX_CTI_AP_STS */
#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_CTI_AP_STS_VAL_MASK 0xFF

/* ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL */
#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_SHIFT 0
#define ARC_FARM_ARC0_AUX_CTI_CFG_MUX_SEL_RUN_HALT_MASK 0x1

/* ARC_FARM_ARC0_AUX_ARC_RST */
#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_SHIFT 0
#define ARC_FARM_ARC0_AUX_ARC_RST_CORE_MASK 0x1
#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_SHIFT 4
#define ARC_FARM_ARC0_AUX_ARC_RST_PRESETDBGN_MASK 0x10

/* ARC_FARM_ARC0_AUX_ARC_RST_REQ */
#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_ARC_RST_REQ_VAL_MASK 0x1

/* ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR */
#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_SRAM_LSB_ADDR_VAL_MASK 0x3F

/* ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR */
#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_SHIFT 0
#define ARC_FARM_ARC0_AUX_SRAM_MSB_ADDR_VAL_MASK 0xFFFFFFFF

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.