drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/cpu_if_regs.h- Extension
.h- Size
- 18149 bytes
- Lines
- 778
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_CPU_IF_REGS_H_
#define ASIC_REG_CPU_IF_REGS_H_
/*
*****************************************
* CPU_IF
* (Prototype: CPU_IF)
*****************************************
*/
#define mmCPU_IF_ARUSER_OVR 0x4CC1104
#define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108
#define mmCPU_IF_AWUSER_OVR 0x4CC110C
#define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110
#define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114
#define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120
#define mmCPU_IF_AXCACHE_OVR 0x4CC1128
#define mmCPU_IF_LOCK_OVR 0x4CC112C
#define mmCPU_IF_PROT_OVR 0x4CC1130
#define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134
#define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138
#define mmCPU_IF_FORCE_RSP_OK 0x4CC113C
#define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140
#define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144
#define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148
#define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C
#define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150
#define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154
#define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158
#define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C
#define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160
#define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164
#define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168
#define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C
#define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170
#define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174
#define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188
#define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C
#define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0
#define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4
#define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8
#define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC
#define mmCPU_IF_PF_PQ_PI 0x4CC1200
#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204
#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208
#define mmCPU_IF_PQ_LENGTH 0x4CC120C
#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210
#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214
#define mmCPU_IF_CQ_LENGTH 0x4CC1218
#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.