drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_masks.h

Extension

.h

Size

17899 bytes

Lines

416

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_
#define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_

/*
 *****************************************
 *   DCORE0_EDMA0_CORE
 *   (Prototype: DMA_CORE)
 *****************************************
 */

/* DCORE0_EDMA0_CORE_CFG_0 */
#define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0
#define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1

/* DCORE0_EDMA0_CORE_CFG_1 */
#define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0
#define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1
#define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2

/* DCORE0_EDMA0_CORE_PROT */
#define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1
#define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2

/* DCORE0_EDMA0_CORE_CKG */
#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
#define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1
#define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2
#define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2
#define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4

/* DCORE0_EDMA0_CORE_RD_GLBL */
#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4
#define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10
#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5
#define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20

/* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF

/* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16
#define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000

/* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */
#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF

/* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */
#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31
#define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000

/* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF

/* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16
#define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000

/* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */
#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF

/* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */
#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF

/* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */
#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0
#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF
#define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.