drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_regs.h

Extension

.h

Size

4167 bytes

Lines

158

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_
#define ASIC_REG_DCORE0_EDMA0_CORE_REGS_H_

/*
 *****************************************
 *   DCORE0_EDMA0_CORE
 *   (Prototype: DMA_CORE)
 *****************************************
 */

#define mmDCORE0_EDMA0_CORE_CFG_0 0x41CB000

#define mmDCORE0_EDMA0_CORE_CFG_1 0x41CB004

#define mmDCORE0_EDMA0_CORE_PROT 0x41CB008

#define mmDCORE0_EDMA0_CORE_CKG 0x41CB00C

#define mmDCORE0_EDMA0_CORE_RD_GLBL 0x41CB07C

#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x41CB080

#define mmDCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE 0x41CB084

#define mmDCORE0_EDMA0_CORE_RD_HBW_ARCACHE 0x41CB088

#define mmDCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS 0x41CB090

#define mmDCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x41CB094

#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x41CB0C0

#define mmDCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE 0x41CB0C4

#define mmDCORE0_EDMA0_CORE_RD_LBW_ARCACHE 0x41CB0C8

#define mmDCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS 0x41CB0D0

#define mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x41CB0D4

#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x41CB100

#define mmDCORE0_EDMA0_CORE_WR_HBW_MAX_AWID 0x41CB104

#define mmDCORE0_EDMA0_CORE_WR_HBW_AWCACHE 0x41CB108

#define mmDCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS 0x41CB10C

#define mmDCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x41CB110

#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x41CB140

#define mmDCORE0_EDMA0_CORE_WR_LBW_MAX_AWID 0x41CB144

#define mmDCORE0_EDMA0_CORE_WR_LBW_AWCACHE 0x41CB148

#define mmDCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS 0x41CB14C

#define mmDCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x41CB150

#define mmDCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x41CB180

#define mmDCORE0_EDMA0_CORE_WR_COMP_AWUSER 0x41CB184

#define mmDCORE0_EDMA0_CORE_ERR_CFG 0x41CB300

#define mmDCORE0_EDMA0_CORE_ERR_CAUSE 0x41CB304

#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_LO 0x41CB308

#define mmDCORE0_EDMA0_CORE_ERRMSG_ADDR_HI 0x41CB30C

#define mmDCORE0_EDMA0_CORE_ERRMSG_WDATA 0x41CB310

#define mmDCORE0_EDMA0_CORE_STS0 0x41CB380

#define mmDCORE0_EDMA0_CORE_STS1 0x41CB384

#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SEL 0x41CB400

#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_SIZE 0x41CB404

#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO 0x41CB408

#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI 0x41CB40C

#define mmDCORE0_EDMA0_CORE_STS_RD_CTX_ID 0x41CB410

#define mmDCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x41CB414

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.