drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_qm_regs.h
Extension
.h
Size
28932 bytes
Lines
1058
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_EDMA0_QM_REGS_H_
#define ASIC_REG_DCORE0_EDMA0_QM_REGS_H_

/*
 *****************************************
 *   DCORE0_EDMA0_QM
 *   (Prototype: QMAN)
 *****************************************
 */

#define mmDCORE0_EDMA0_QM_GLBL_CFG0 0x41CA000

#define mmDCORE0_EDMA0_QM_GLBL_CFG1 0x41CA004

#define mmDCORE0_EDMA0_QM_GLBL_CFG2 0x41CA008

#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG 0x41CA00C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_CFG1 0x41CA010

#define mmDCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x41CA014

#define mmDCORE0_EDMA0_QM_GLBL_AXCACHE 0x41CA018

#define mmDCORE0_EDMA0_QM_GLBL_STS0 0x41CA01C

#define mmDCORE0_EDMA0_QM_GLBL_STS1 0x41CA020

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_0 0x41CA024

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_1 0x41CA028

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_2 0x41CA02C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_3 0x41CA030

#define mmDCORE0_EDMA0_QM_GLBL_ERR_STS_4 0x41CA034

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_0 0x41CA038

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_1 0x41CA03C

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_2 0x41CA040

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_3 0x41CA044

#define mmDCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 0x41CA048

#define mmDCORE0_EDMA0_QM_GLBL_PROT 0x41CA04C

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_0 0x41CA050

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_1 0x41CA054

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_2 0x41CA058

#define mmDCORE0_EDMA0_QM_PQ_BASE_LO_3 0x41CA05C

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_0 0x41CA060

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_1 0x41CA064

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_2 0x41CA068

#define mmDCORE0_EDMA0_QM_PQ_BASE_HI_3 0x41CA06C

#define mmDCORE0_EDMA0_QM_PQ_SIZE_0 0x41CA070

#define mmDCORE0_EDMA0_QM_PQ_SIZE_1 0x41CA074

#define mmDCORE0_EDMA0_QM_PQ_SIZE_2 0x41CA078

#define mmDCORE0_EDMA0_QM_PQ_SIZE_3 0x41CA07C

#define mmDCORE0_EDMA0_QM_PQ_PI_0 0x41CA080

#define mmDCORE0_EDMA0_QM_PQ_PI_1 0x41CA084

#define mmDCORE0_EDMA0_QM_PQ_PI_2 0x41CA088

#define mmDCORE0_EDMA0_QM_PQ_PI_3 0x41CA08C

#define mmDCORE0_EDMA0_QM_PQ_CI_0 0x41CA090

#define mmDCORE0_EDMA0_QM_PQ_CI_1 0x41CA094

#define mmDCORE0_EDMA0_QM_PQ_CI_2 0x41CA098

#define mmDCORE0_EDMA0_QM_PQ_CI_3 0x41CA09C

Annotation

Implementation Notes