drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h

Extension

.h

Size

13345 bytes

Lines

290

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_
#define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_

/*
 *****************************************
 *   DCORE0_HMMU0_MMU
 *   (Prototype: MMU)
 *****************************************
 */

/* DCORE0_HMMU0_MMU_MMU_ENABLE */
#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0
#define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1

/* DCORE0_HMMU0_MMU_FORCE_ORDERING */
#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0
#define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1
#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1
#define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2

/* DCORE0_HMMU0_MMU_FEATURE_ENABLE */
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7
#define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80

/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */
#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0
#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF

/* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */
#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0
#define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF

/* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */
#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0
#define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF

/* DCORE0_HMMU0_MMU_SCRAMBLER */
#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0
#define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F
#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6
#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40
#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7
#define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80
#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8
#define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00

/* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3
#define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8

/* DCORE0_HMMU0_MMU_SPI_SEI_MASK */
#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0
#define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF

/* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */
#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0
#define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF

/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */
#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0
#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF

/* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */
#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0
#define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF

/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */
#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0
#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF

/* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */
#define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.