drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_regs.h
Extension
.h
Size
6841 bytes
Lines
238
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_
#define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_

/*
 *****************************************
 *   DCORE0_HMMU0_MMU
 *   (Prototype: MMU)
 *****************************************
 */

#define mmDCORE0_HMMU0_MMU_MMU_ENABLE 0x408000C

#define mmDCORE0_HMMU0_MMU_FORCE_ORDERING 0x4080010

#define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE 0x4080014

#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 0x4080018

#define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 0x408001C

#define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE 0x4080020

#define mmDCORE0_HMMU0_MMU_SCRAMBLER 0x4080024

#define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY 0x4080028

#define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK 0x408002C

#define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE 0x4080030

#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE 0x4080034

#define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA 0x4080038

#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE 0x408003C

#define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA 0x4080040

#define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID 0x4080044

#define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR 0x4080048

#define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK 0x408004C

#define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM 0x4080050

#define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR 0x4080054

#define mmDCORE0_HMMU0_MMU_PIPE_CREDIT 0x4080058

#define mmDCORE0_HMMU0_MMU_MMU_BYPASS 0x408006C

#define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE 0x4080070

#define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG 0x40800A0

#define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT 0x40800D0

#define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT 0x40800F4

#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB 0x40800F8

#define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB 0x40800FC

#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB 0x4080100

#define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB 0x4080104

#define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE 0x4080108

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 0x4080110

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 0x4080114

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 0x4080118

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 0x408011C

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 0x4080120

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 0x4080124

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 0x4080128

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 0x408012C

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 0x4080140

#define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 0x4080144

Annotation

Implementation Notes