drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_regs.h
Extension
.h
Size
4011 bytes
Lines
142
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_
#define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_

/*
 *****************************************
 *   DCORE0_HMMU0_STLB
 *   (Prototype: STLB)
 *****************************************
 */

#define mmDCORE0_HMMU0_STLB_BUSY 0x4081000

#define mmDCORE0_HMMU0_STLB_ASID 0x4081004

#define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 0x4081008

#define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 0x408100C

#define mmDCORE0_HMMU0_STLB_CACHE_INV 0x4081010

#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 0x4081014

#define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 0x4081018

#define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN 0x408101C

#define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE 0x4081020

#define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION 0x4081024

#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4081028

#define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x408102C

#define mmDCORE0_HMMU0_STLB_INV_ALL_START 0x4081034

#define mmDCORE0_HMMU0_STLB_INV_ALL_SET 0x4081038

#define mmDCORE0_HMMU0_STLB_INV_PS 0x408103C

#define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX 0x4081040

#define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT 0x4081044

#define mmDCORE0_HMMU0_STLB_INV_SET 0x4081048

#define mmDCORE0_HMMU0_STLB_SRAM_INIT 0x408104C

#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION 0x4081050

#define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS 0x4081054

#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 0x4081058

#define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 0x408105C

#define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG 0x4081060

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 0x4081064

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 0x4081068

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 0x408106C

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 0x4081070

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 0x4081074

#define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 0x4081078

#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR 0x408107C

#define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK 0x4081080

#define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG 0x4081084

#define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT 0x4081088

#define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION 0x408108C

#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB 0x4081090

#define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB 0x4081094

#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB 0x4081098

#define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB 0x408109C

#define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL 0x4081100

Annotation

Implementation Notes