drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_regs.h
Extension
.h
Size
4447 bytes
Lines
164
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_

/*
 *****************************************
 *   DCORE0_MME_CTRL_LO
 *   (Prototype: MME_CTRL_LO)
 *****************************************
 */

#define mmDCORE0_MME_CTRL_LO_ARCH_STATUS 0x40CB000

#define mmDCORE0_MME_CTRL_LO_CMD 0x40CB004

#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x40CB148

#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x40CB14C

#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x40CB150

#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x40CB154

#define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x40CB158

#define mmDCORE0_MME_CTRL_LO_ARCH_A_SS 0x40CB224

#define mmDCORE0_MME_CTRL_LO_ARCH_B_SS 0x40CB228

#define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS 0x40CB27C

#define mmDCORE0_MME_CTRL_LO_QM_STALL 0x40CB400

#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO 0x40CB404

#define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI 0x40CB408

#define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x40CB40C

#define mmDCORE0_MME_CTRL_LO_REDUN 0x40CB410

#define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x40CB414

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x40CB418

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x40CB41C

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x40CB420

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x40CB424

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x40CB428

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x40CB42C

#define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x40CB430

#define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 0x40CB434

#define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x40CB438

#define mmDCORE0_MME_CTRL_LO_PCU_RL_TH 0x40CB43C

#define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN 0x40CB440

#define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN 0x40CB444

#define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x40CB448

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x40CB44C

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x40CB450

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x40CB454

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x40CB458

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 0x40CB45C

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x40CB460

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x40CB464

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x40CB468

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x40CB46C

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x40CB470

#define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x40CB474

Annotation

Implementation Notes