drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_arc_aux_regs.h
Extension
.h
Size
18167 bytes
Lines
592
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_
#define ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_

/*
 *****************************************
 *   DCORE0_MME_QM_ARC_AUX
 *   (Prototype: QMAN_ARC_AUX)
 *****************************************
 */

#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ 0x40C8100

#define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK 0x40C8104

#define mmDCORE0_MME_QM_ARC_AUX_RST_VEC_ADDR 0x40C8108

#define mmDCORE0_MME_QM_ARC_AUX_DBG_MODE 0x40C810C

#define mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM 0x40C8110

#define mmDCORE0_MME_QM_ARC_AUX_ARC_NUM 0x40C8114

#define mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT 0x40C8118

#define mmDCORE0_MME_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x40C811C

#define mmDCORE0_MME_QM_ARC_AUX_CTI_AP_STS 0x40C8120

#define mmDCORE0_MME_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x40C8124

#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST 0x40C8128

#define mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ 0x40C812C

#define mmDCORE0_MME_QM_ARC_AUX_SRAM_LSB_ADDR 0x40C8130

#define mmDCORE0_MME_QM_ARC_AUX_SRAM_MSB_ADDR 0x40C8134

#define mmDCORE0_MME_QM_ARC_AUX_PCIE_LSB_ADDR 0x40C8138

#define mmDCORE0_MME_QM_ARC_AUX_PCIE_MSB_ADDR 0x40C813C

#define mmDCORE0_MME_QM_ARC_AUX_CFG_LSB_ADDR 0x40C8140

#define mmDCORE0_MME_QM_ARC_AUX_CFG_MSB_ADDR 0x40C8144

#define mmDCORE0_MME_QM_ARC_AUX_HBM0_LSB_ADDR 0x40C8150

#define mmDCORE0_MME_QM_ARC_AUX_HBM0_MSB_ADDR 0x40C8154

#define mmDCORE0_MME_QM_ARC_AUX_HBM1_LSB_ADDR 0x40C8158

#define mmDCORE0_MME_QM_ARC_AUX_HBM1_MSB_ADDR 0x40C815C

#define mmDCORE0_MME_QM_ARC_AUX_HBM2_LSB_ADDR 0x40C8160

#define mmDCORE0_MME_QM_ARC_AUX_HBM2_MSB_ADDR 0x40C8164

#define mmDCORE0_MME_QM_ARC_AUX_HBM3_LSB_ADDR 0x40C8168

#define mmDCORE0_MME_QM_ARC_AUX_HBM3_MSB_ADDR 0x40C816C

#define mmDCORE0_MME_QM_ARC_AUX_HBM0_OFFSET 0x40C8170

#define mmDCORE0_MME_QM_ARC_AUX_HBM1_OFFSET 0x40C8174

#define mmDCORE0_MME_QM_ARC_AUX_HBM2_OFFSET 0x40C8178

#define mmDCORE0_MME_QM_ARC_AUX_HBM3_OFFSET 0x40C817C

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x40C8180

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x40C8184

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x40C8188

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x40C818C

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x40C8190

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x40C8194

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x40C8198

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x40C819C

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40C81A0

#define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40C81A4

Annotation

Implementation Notes