drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h
Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_qm_regs.h- Extension
.h- Size
- 27890 bytes
- Lines
- 1058
- Domain
- Driver Families
- Bucket
- drivers/accel
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_
#define ASIC_REG_DCORE0_MME_QM_REGS_H_
/*
*****************************************
* DCORE0_MME_QM
* (Prototype: QMAN)
*****************************************
*/
#define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000
#define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004
#define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008
#define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C
#define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010
#define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014
#define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018
#define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C
#define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020
#define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024
#define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028
#define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C
#define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030
#define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044
#define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048
#define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C
#define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050
#define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054
#define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058
#define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C
#define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060
#define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064
#define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068
#define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C
#define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070
#define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074
#define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078
#define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C
#define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080
#define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084
#define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088
#define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C
#define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090
#define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094
#define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098
#define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C
Annotation
- Atlas domain: Driver Families / drivers/accel.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.