drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_ctrl_regs.h
Extension
.h
Size
8091 bytes
Lines
292
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_
#define ASIC_REG_DCORE0_RTR0_CTRL_REGS_H_

/*
 *****************************************
 *   DCORE0_RTR0_CTRL
 *   (Prototype: RTR_CTRL)
 *****************************************
 */

#define mmDCORE0_RTR0_CTRL_MEM_NUM 0x4140100

#define mmDCORE0_RTR0_CTRL_MEM_MAP 0x4140104

#define mmDCORE0_RTR0_CTRL_WR_RL_MEM 0x4140108

#define mmDCORE0_RTR0_CTRL_WR_RL_PCI 0x414010C

#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM 0x4140110

#define mmDCORE0_RTR0_CTRL_RD_RL_MEM 0x4140114

#define mmDCORE0_RTR0_CTRL_RD_RL_PCI 0x4140118

#define mmDCORE0_RTR0_CTRL_RD_RL_SRAM 0x414011C

#define mmDCORE0_RTR0_CTRL_WR_RL_MEM_RED 0x4140120

#define mmDCORE0_RTR0_CTRL_RL_MEM_REDUCTION 0x4140124

#define mmDCORE0_RTR0_CTRL_WR_RL_SRAM_RED 0x4140128

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_0 0x4140400

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_CFG_1 0x4140404

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_0 0x4140408

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_SHIFT_1 0x414040C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_0 0x4140410

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_1 0x4140414

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_2 0x4140418

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_3 0x414041C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_4 0x4140420

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_5 0x4140424

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_6 0x4140428

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_7 0x414042C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_8 0x4140430

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_9 0x4140434

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_10 0x4140438

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_11 0x414043C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_12 0x4140440

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_13 0x4140444

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_14 0x4140448

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_EXPECTED_LAT_15 0x414044C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_0 0x4140450

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_1 0x4140454

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_2 0x4140458

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_3 0x414045C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_4 0x4140460

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_5 0x4140464

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_6 0x4140468

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_7 0x414046C

#define mmDCORE0_RTR0_CTRL_RGL_SRAM_TOKEN_8 0x4140470

Annotation

Implementation Notes