drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h

Extension

.h

Size

7682 bytes

Lines

214

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_
#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_REGS_H_

/*
 *****************************************
 *   DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW
 *   (Prototype: RANGE_REG_HBW)
 *****************************************
 */

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142200

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142204

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142208

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414220C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142210

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142214

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142218

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414221C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142220

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142224

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142228

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414222C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142230

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142234

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142238

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414223C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142240

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142244

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142248

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414224C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142250

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142254

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142258

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414225C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142260

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142264

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142268

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414226C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142270

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142274

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142278

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414227C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142280

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142284

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142288

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414228C

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142290

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142294

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142298

#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414229C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.