drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h

Extension

.h

Size

7682 bytes

Lines

214

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_
#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_

/*
 *****************************************
 *   DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW
 *   (Prototype: RANGE_REG_HBW)
 *****************************************
 */

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142000

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142004

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142008

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414200C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142010

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142014

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142018

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414201C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142020

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142024

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142028

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414202C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142030

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142034

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142038

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414203C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142040

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142044

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142048

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414204C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142050

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142054

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142058

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414205C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142060

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142064

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142068

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414206C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142070

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142074

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142078

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414207C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142080

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142084

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142088

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414208C

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142090

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142094

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142098

#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414209C

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.