drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h

Extension

.h

Size

22268 bytes

Lines

510

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG
 *   (Prototype: TPC)
 *****************************************
 */

/* DCORE0_TPC0_CFG_TPC_COUNT */
#define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0
#define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF

/* DCORE0_TPC0_CFG_TPC_ID */
#define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0
#define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF

/* DCORE0_TPC0_CFG_STALL_ON_ERR */
#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0
#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1

/* DCORE0_TPC0_CFG_CLK_EN */
#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0
#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1
#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4
#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10

/* DCORE0_TPC0_CFG_IQ_RL_EN */
#define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0
#define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1

/* DCORE0_TPC0_CFG_IQ_RL_SAT */
#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0
#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF

/* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */
#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0
#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF

/* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */
#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0
#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF

/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */
#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0
#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF

/* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */
#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0
#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1

/* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */
#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0
#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF

/* DCORE0_TPC0_CFG_TPC_LOCK */
#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0
#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1

/* DCORE0_TPC0_CFG_CGU_SB */
#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0
#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1

/* DCORE0_TPC0_CFG_CGU_CNT */
#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0
#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1
#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1
#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11
#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800
#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.