drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h

Extension

.h

Size

3272 bytes

Lines

130

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG_QM
 *   (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
 *****************************************
 */

#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4

#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8

#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC

#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0

#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4

#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8

#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC

#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00

#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04

#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08

#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C

#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10

#define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14

#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18

#define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C

#define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20

#define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24

#define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28

#define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C

#define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30

#define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34

#define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38

#define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C

#define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40

#define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44

#define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48

#define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C

#define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50

#define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54

#define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58

#define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C

#define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60

#define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64

#define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68

#define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C

#define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70

#define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74

#define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78

#define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C

#define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.