drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_regs.h

Extension

.h

Size

5995 bytes

Lines

230

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_CFG_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG
 *   (Prototype: TPC)
 *****************************************
 */

#define mmDCORE0_TPC0_CFG_TPC_COUNT 0x400BC18

#define mmDCORE0_TPC0_CFG_TPC_ID 0x400BC1C

#define mmDCORE0_TPC0_CFG_STALL_ON_ERR 0x400BC20

#define mmDCORE0_TPC0_CFG_CLK_EN 0x400BC24

#define mmDCORE0_TPC0_CFG_IQ_RL_EN 0x400BC28

#define mmDCORE0_TPC0_CFG_IQ_RL_SAT 0x400BC2C

#define mmDCORE0_TPC0_CFG_IQ_RL_RST_TOKEN 0x400BC30

#define mmDCORE0_TPC0_CFG_IQ_RL_TIMEOUT 0x400BC34

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_0 0x400BC38

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_1 0x400BC3C

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_2 0x400BC40

#define mmDCORE0_TPC0_CFG_TSB_CFG_MTRR_2_3 0x400BC44

#define mmDCORE0_TPC0_CFG_IQ_LBW_CLK_EN 0x400BC48

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0 0x400BC4C

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 0x400BC50

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_2 0x400BC54

#define mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_3 0x400BC58

#define mmDCORE0_TPC0_CFG_TPC_LOCK_0 0x400BC5C

#define mmDCORE0_TPC0_CFG_TPC_LOCK_1 0x400BC60

#define mmDCORE0_TPC0_CFG_TPC_LOCK_2 0x400BC64

#define mmDCORE0_TPC0_CFG_TPC_LOCK_3 0x400BC68

#define mmDCORE0_TPC0_CFG_CGU_SB 0x400BC6C

#define mmDCORE0_TPC0_CFG_CGU_CNT 0x400BC70

#define mmDCORE0_TPC0_CFG_CGU_CPE_0 0x400BC74

#define mmDCORE0_TPC0_CFG_CGU_CPE_1 0x400BC78

#define mmDCORE0_TPC0_CFG_CGU_CPE_2 0x400BC7C

#define mmDCORE0_TPC0_CFG_CGU_CPE_3 0x400BC80

#define mmDCORE0_TPC0_CFG_CGU_CPE_4 0x400BC84

#define mmDCORE0_TPC0_CFG_CGU_CPE_5 0x400BC88

#define mmDCORE0_TPC0_CFG_CGU_CPE_6 0x400BC8C

#define mmDCORE0_TPC0_CFG_CGU_CPE_7 0x400BC90

#define mmDCORE0_TPC0_CFG_FP16_FTZ_IN 0x400BC94

#define mmDCORE0_TPC0_CFG_DCACHE_CFG 0x400BC98

#define mmDCORE0_TPC0_CFG_E2E_CRDT_TOP 0x400BC9C

#define mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD 0x400BCA0

#define mmDCORE0_TPC0_CFG_TPC_SB_L0CD 0x400BCA4

#define mmDCORE0_TPC0_CFG_CONV_ROUND_CSR 0x400BCA8

#define mmDCORE0_TPC0_CFG_TSB_OCCUPANCY 0x400BCAC

#define mmDCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT 0x400BCB0

#define mmDCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT 0x400BCB4

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.