drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h

Source file repositories/reference/linux-study-clean/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_special_regs.h
Extension
.h
Size
5228 bytes
Lines
186
Domain
Driver Families
Bucket
drivers/accel
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_
#define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_CFG_SPECIAL
 *   (Prototype: SPECIAL_REGS)
 *****************************************
 */

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8

#define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C

#define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20

Annotation

Implementation Notes