drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_etf_regs.h

Extension

.h

Size

2614 bytes

Lines

114

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_
#define ASIC_REG_DCORE0_TPC0_EML_ETF_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_EML_ETF
 *   (Prototype: ETF_1KB)
 *****************************************
 */

#define mmDCORE0_TPC0_EML_ETF_RSZ 0x2004

#define mmDCORE0_TPC0_EML_ETF_STS 0x200C

#define mmDCORE0_TPC0_EML_ETF_RRD 0x2010

#define mmDCORE0_TPC0_EML_ETF_RRP 0x2014

#define mmDCORE0_TPC0_EML_ETF_RWP 0x2018

#define mmDCORE0_TPC0_EML_ETF_TRG 0x201C

#define mmDCORE0_TPC0_EML_ETF_CTL 0x2020

#define mmDCORE0_TPC0_EML_ETF_RWD 0x2024

#define mmDCORE0_TPC0_EML_ETF_MODE 0x2028

#define mmDCORE0_TPC0_EML_ETF_LBUFLEVEL 0x202C

#define mmDCORE0_TPC0_EML_ETF_CBUFLEVEL 0x2030

#define mmDCORE0_TPC0_EML_ETF_BUFWM 0x2034

#define mmDCORE0_TPC0_EML_ETF_FFSR 0x2300

#define mmDCORE0_TPC0_EML_ETF_FFCR 0x2304

#define mmDCORE0_TPC0_EML_ETF_PSCR 0x2308

#define mmDCORE0_TPC0_EML_ETF_ITATBMDATA0 0x2ED0

#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR2 0x2ED4

#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR1 0x2ED8

#define mmDCORE0_TPC0_EML_ETF_ITATBMCTR0 0x2EDC

#define mmDCORE0_TPC0_EML_ETF_ITMISCOP0 0x2EE0

#define mmDCORE0_TPC0_EML_ETF_ITTRFLIN 0x2EE8

#define mmDCORE0_TPC0_EML_ETF_ITATBDATA0 0x2EEC

#define mmDCORE0_TPC0_EML_ETF_ITATBCTR2 0x2EF0

#define mmDCORE0_TPC0_EML_ETF_ITATBCTR1 0x2EF4

#define mmDCORE0_TPC0_EML_ETF_ITATBCTR0 0x2EF8

#define mmDCORE0_TPC0_EML_ETF_ITCTRL 0x2F00

#define mmDCORE0_TPC0_EML_ETF_CLAIMSET 0x2FA0

#define mmDCORE0_TPC0_EML_ETF_CLAIMCLR 0x2FA4

#define mmDCORE0_TPC0_EML_ETF_LAR 0x2FB0

#define mmDCORE0_TPC0_EML_ETF_LSR 0x2FB4

#define mmDCORE0_TPC0_EML_ETF_AUTHSTATUS 0x2FB8

#define mmDCORE0_TPC0_EML_ETF_DEVID 0x2FC8

#define mmDCORE0_TPC0_EML_ETF_DEVTYPE 0x2FCC

#define mmDCORE0_TPC0_EML_ETF_PERIPHID4 0x2FD0

#define mmDCORE0_TPC0_EML_ETF_PERIPHID5 0x2FD4

#define mmDCORE0_TPC0_EML_ETF_PERIPHID6 0x2FD8

#define mmDCORE0_TPC0_EML_ETF_PERIPHID7 0x2FDC

#define mmDCORE0_TPC0_EML_ETF_PERIPHID0 0x2FE0

#define mmDCORE0_TPC0_EML_ETF_PERIPHID1 0x2FE4

#define mmDCORE0_TPC0_EML_ETF_PERIPHID2 0x2FE8

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.