drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h

File Facts

System

Linux kernel

Corpus path

drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_funnel_regs.h

Extension

.h

Size

1852 bytes

Lines

76

Domain

Driver Families

Bucket

drivers/accel

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_
#define ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_

/*
 *****************************************
 *   DCORE0_TPC0_EML_FUNNEL
 *   (Prototype: FUNNEL_2X1)
 *****************************************
 */

#define mmDCORE0_TPC0_EML_FUNNEL_CTRL_REG 0x6000

#define mmDCORE0_TPC0_EML_FUNNEL_PRIORITY_CTRL_REG 0x6004

#define mmDCORE0_TPC0_EML_FUNNEL_ITATBDATA0 0x6EEC

#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR2 0x6EF0

#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR1 0x6EF4

#define mmDCORE0_TPC0_EML_FUNNEL_ITATBCTR0 0x6EF8

#define mmDCORE0_TPC0_EML_FUNNEL_ITCTRL 0x6F00

#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMSET 0x6FA0

#define mmDCORE0_TPC0_EML_FUNNEL_CLAIMCLR 0x6FA4

#define mmDCORE0_TPC0_EML_FUNNEL_LOCKACCESS 0x6FB0

#define mmDCORE0_TPC0_EML_FUNNEL_LOCKSTATUS 0x6FB4

#define mmDCORE0_TPC0_EML_FUNNEL_AUTHSTATUS 0x6FB8

#define mmDCORE0_TPC0_EML_FUNNEL_DEVID 0x6FC8

#define mmDCORE0_TPC0_EML_FUNNEL_DEVTYPE 0x6FCC

#define mmDCORE0_TPC0_EML_FUNNEL_PIDR4 0x6FD0

#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID5 0x6FD4

#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID6 0x6FD8

#define mmDCORE0_TPC0_EML_FUNNEL_PERIPHID7 0x6FDC

#define mmDCORE0_TPC0_EML_FUNNEL_PIDR0 0x6FE0

#define mmDCORE0_TPC0_EML_FUNNEL_PIDR1 0x6FE4

#define mmDCORE0_TPC0_EML_FUNNEL_PIDR2 0x6FE8

#define mmDCORE0_TPC0_EML_FUNNEL_PIDR3 0x6FEC

#define mmDCORE0_TPC0_EML_FUNNEL_CID0 0x6FF0

#define mmDCORE0_TPC0_EML_FUNNEL_CID1 0x6FF4

#define mmDCORE0_TPC0_EML_FUNNEL_CID2 0x6FF8

#define mmDCORE0_TPC0_EML_FUNNEL_CID3 0x6FFC

#endif /* ASIC_REG_DCORE0_TPC0_EML_FUNNEL_REGS_H_ */

Annotation

• Atlas domain: Driver Families / drivers/accel.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.